Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor

ABSTRACT

Monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by the processor. The processor executes a transactional memory (TM) transaction, including receiving, by the processor, a memory address range of data that a co-processor may access to perform a co-processor operation. The processor saves the memory address range. Based on receiving, by the processor, a cache coherency request that conflicts with the saved address range, the processor aborts the TM transaction.

BACKGROUND

This disclosure relates generally to the field of cache coherency, andmore particularly to monitoring locations accessed by a co-processorduring transactional execution of a processor that are not in theread-set or write-set of the transaction.

The number of central processing unit (CPU) cores on a chip and thenumber of CPU cores connected to a shared memory continues to growsignificantly to support growing workload capacity demand. Theincreasing number of CPUs cooperating to process the same workloads putsa significant burden on software scalability; for example, shared queuesor data-structures protected by traditional semaphores become hot spotsand lead to sub-linear n-way scaling curves. Traditionally this has beencountered by implementing finer-grained locking in software, and withlower latency/higher bandwidth interconnects in hardware. Implementingfine-grained locking to improve software scalability can be verycomplicated and error-prone, and at today's CPU frequencies, thelatencies of hardware interconnects are limited by the physicaldimension of the chips and systems, and by the speed of light.

Implementations of hardware Transactional Memory (HTM, or in thisdiscussion, simply TM) have been introduced, wherein a group ofinstructions—called a transaction—operate in an atomic manner on a datastructure in memory, as viewed by other central processing units (CPUs)and the I/O subsystem (atomic operation is also known as “blockconcurrent” or “serialized” in other literature). The transactionexecutes optimistically without obtaining a lock, but may need to abortand retry the transaction execution if an operation, of the executingtransaction, on a memory location conflicts with another operation onthe same memory location. Previously, software transactional memoryimplementations have been proposed to support software TransactionalMemory (TM). However, hardware TM can provide improved performanceaspects and ease of use over software TM.

A co-processor is a computer processor used to supplement the functionsof the primary processor, the CPU. A co-processor offloads specializedprocessing operations, thereby reducing the burden on the basic CPUcircuitry and allowing it to work at optimum speed. By offloadingprocessor-intensive tasks from the main processor, co-processors canaccelerate system performance. Operations performed by a co-processormay include floating point arithmetic, graphics, signal processing,string processing, encryption, compression, or I/O interfacing withperipheral devices.

An encryption co-processor may be a dedicated computer on a chip ormicroprocessor for carrying out cryptographic operations, embedded in apackaging with multiple physical security measures, which give it adegree of tamper resistance. Unlike encryption co-processors that outputdecrypted data onto a bus in a secure environment, a secure encryptionco-processor does not output decrypted data or decrypted programinstructions in an environment where security cannot always bemaintained. Secure encryption co-processors may output decrypted data ordecrypted program instructions into memory or cache locations within thesecure encryption co-processor, which may be fetched by the CPU viadirect memory accesses.

SUMMARY

Embodiments of the disclosure describe a method, computer programproduct, and system for monitoring, by a processor having a cache,addresses accessed by a co-processor associated with the processorduring transactional execution of a transaction by the processor. Theprocessor executes a transactional memory (TM) transaction, includingreceiving, by the processor, a memory address range of data that aco-processor may access to perform a co-processor operation. Theprocessor saves the memory address range. Based on receiving, by theprocessor, a cache coherency request that conflicts with the savedaddress range, the processor aborts the TM transaction.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

One or more aspects of the present disclosure are particularly pointedout and distinctly claimed as examples in the claims at the conclusionof the specification. The foregoing and other objects, features, andadvantages of the disclosure are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 depicts a functional block diagram of a multicore transactionalmemory environment, in accordance with embodiments of the presentdisclosure;

FIG. 2 depicts a functional block diagram of a CPU core of the multicoreTransactional Memory environment of FIG. 1, in accordance withembodiments of the present disclosure;

FIG. 3 depicts a functional block diagram of components of a CPU, inaccordance with embodiments of the present disclosure;

FIG. 4 depicts a functional block diagram of a second multicoretransactional memory environment, in accordance with embodiments of thepresent disclosure;

FIG. 5 is a flowchart depicting operational steps for monitoring memoryaddresses accessed by co-processor, in accordance with an embodiment ofthe disclosure;

FIG. 6 is a functional block diagram of components of a CPU environmentand a co-processor, in accordance with an embodiment of the disclosure;

FIG. 7 is a schematic block diagram of components of a CPU environmentand a co-processor, in accordance with an embodiment of the disclosure;

FIG. 8 is a flowchart depicting operational steps for performingtransactional stores by a co-processor associated with a CPU executingthe transaction, in accordance with an embodiment of the disclosure;

FIG. 9 is a flowchart depicting operational steps for monitoringaddresses accessed by a co-processor associated with the processorduring transactional execution of a transaction by the processor, inaccordance with an embodiment of the disclosure; and

FIG. 10 depicts a block diagram of components of an embodiment of acomputing device, in accordance with one or more embodiments of thedisclosure.

DETAILED DESCRIPTION

Historically, a computer system or processor had only a single processor(aka processing unit or central processing unit). The processor includedan instruction processing unit (IPU), a branch unit, a memory controlunit and the like. Such processors were capable of executing a singlethread of a program at a time. Operating systems were developed thatcould time-share a processor by dispatching a program to be executed onthe processor for a period of time, and then dispatching another programto be executed on the processor for another period of time. Astechnology evolved, memory subsystem caches were often added to theprocessor as well as complex dynamic address translation includingtranslation lookaside buffers (TLBs). The IPU itself was often referredto as a processor. As technology continued to evolve, an entireprocessor, could be packaged in a single semiconductor chip or die, sucha processor was referred to as a microprocessor. Then processors weredeveloped that incorporated multiple IPUs, such processors were oftenreferred to as multi-processors. Each such processor of amulti-processor computer system (processor) may include individual orshared caches, memory interfaces, system bus, address translationmechanism and the like. Virtual machine and instruction set architecture(ISA) emulators added a layer of software to a processor, that providedthe virtual machine with multiple “virtual processors” (aka processors)by time-slice usage of a single IPU in a single hardware processor. Astechnology further evolved, multi-threaded processors were developed,enabling a single hardware processor having a single multi-thread IPU toprovide a capability of simultaneously executing threads of differentprograms, thus each thread of a multi-threaded processor appeared to theoperating system as a processor. As technology further evolved, it waspossible to put multiple processors (each having an IPU) on a singlesemiconductor chip or die. These processors were referred to processorcores or just cores. Thus the terms such as processor, centralprocessing unit, processing unit, microprocessor, core, processor core,processor thread, and thread, for example, are often usedinterchangeably. Aspects of embodiments herein may be practiced by anyor all processors including those shown supra, without departing fromthe teachings herein. Wherein the term “thread” or “processor thread” isused herein, it is expected that particular advantage of the embodimentmay be had in a processor thread implementation.

Transaction Execution in Intel® Based Embodiments

In “Intel® Architecture Instruction Set Extensions ProgrammingReference” 319433-012A, February 2012, incorporated herein by referencein its entirety, Chapter 8 teaches, in part, that multithreadedapplications may take advantage of increasing numbers of CPU cores toachieve higher performance. However, the writing of multi-threadedapplications requires programmers to understand and take into accountdata sharing among the multiple threads. Access to shared data typicallyrequires synchronization mechanisms. These synchronization mechanismsare used to ensure that multiple threads update shared data byserializing operations that are applied to the shared data, oftenthrough the use of a critical section that is protected by a lock. Sinceserialization limits concurrency, programmers try to limit the overheaddue to synchronization.

Intel® Transactional Synchronization Extensions (Intel® TSX) allow aprocessor to dynamically determine whether threads need to be serializedthrough lock-protected critical sections, and to perform thatserialization only when required. This allows the processor to exposeand exploit concurrency that is hidden in an application because ofdynamically unnecessary synchronization.

With Intel TSX, programmer-specified code regions (also referred to as“transactional regions” or just “transactions”) are executedtransactionally. If the transactional execution completes successfully,then all memory operations performed within the transactional regionwill appear to have occurred instantaneously when viewed from otherprocessors. A processor makes the memory operations of the executedtransaction, performed within the transactional region, visible to otherprocessors only when a successful commit occurs, i.e., when thetransaction successfully completes execution. This process is oftenreferred to as an atomic commit.

Intel TSX provides two software interfaces to specify regions of codefor transactional execution. Hardware Lock Elision (HLE) is a legacycompatible instruction set extension (comprising the XACQUIRE andXRELEASE prefixes) to specify transactional regions. RestrictedTransactional Memory (RTM) is a new instruction set interface(comprising the XBEGIN, XEND, and XABORT instructions) for programmersto define transactional regions in a more flexible manner than thatpossible with HLE. HLE is for programmers who prefer the backwardcompatibility of the conventional mutual exclusion programming model andwould like to run HLE-enabled software on legacy hardware but would alsolike to take advantage of the new lock elision capabilities on hardwarewith HLE support. RTM is for programmers who prefer a flexible interfaceto the transactional execution hardware. In addition, Intel TSX alsoprovides an XTEST instruction. This instruction allows software to querywhether the logical processor is transactionally executing in atransactional region identified by either HLE or RTM.

Since a successful transactional execution ensures an atomic commit, theprocessor executes the code region optimistically without explicitsynchronization. If synchronization was unnecessary for that specificexecution, execution can commit without any cross-thread serialization.If the processor cannot commit atomically, then the optimistic executionfails. When this happens, the processor will roll back the execution, aprocess referred to as a transactional abort. On a transactional abort,the processor will discard all updates performed in the memory regionused by the transaction, restore architectural state to appear as if theoptimistic execution never occurred, and resume executionnon-transactionally.

A processor can perform a transactional abort for numerous reasons. Aprimary reason to abort a transaction is due to conflicting memoryaccesses between the transactionally executing logical processor andanother logical processor. Such conflicting memory accesses may preventa successful transactional execution. Memory addresses read from withina transactional region constitute the read-set of the transactionalregion and addresses written to within the transactional regionconstitute the write-set of the transactional region. Intel TSXmaintains the read- and write-sets at the granularity of a cache line. Aconflicting memory access occurs if another logical processor eitherreads a location that is part of the transactional region's write-set orwrites a location that is a part of either the read- or write-set of thetransactional region. A conflicting access typically means thatserialization is required for this code region. Since Intel TSX detectsdata conflicts at the granularity of a cache line, unrelated datalocations placed in the same cache line will be detected as conflictsthat result in transactional aborts. Transactional aborts may also occurdue to limited transactional resources. For example, the amount of dataaccessed in the region may exceed an implementation-specific capacity.Additionally, some instructions and system events may causetransactional aborts. Frequent transactional aborts result in wastedcycles and increased inefficiency.

Hardware Lock Elision

Hardware Lock Elision (HLE) provides a legacy compatible instruction setinterface for programmers to use transactional execution. HLE providestwo new instruction prefix hints: XACQUIRE and XRELEASE.

With HLE, a programmer adds the XACQUIRE prefix to the front of theinstruction that is used to acquire the lock that is protecting thecritical section. The processor treats the prefix as a hint to elide thewrite associated with the lock acquire operation. Even though the lockacquire has an associated write operation to the lock, the processordoes not add the address of the lock to the transactional region'swrite-set nor does it issue any write requests to the lock. Instead, theaddress of the lock is added to the read-set. The logical processorenters transactional execution. If the lock was available before theXACQUIRE prefixed instruction, then all other processors will continueto see the lock as available afterwards. Since the transactionallyexecuting logical processor neither added the address of the lock to itswrite-set nor performed externally visible write operations to the lock,other logical processors can read the lock without causing a dataconflict. This allows other logical processors to also enter andconcurrently execute the critical section protected by the lock. Theprocessor automatically detects any data conflicts that occur during thetransactional execution and will perform a transactional abort ifnecessary.

Even though the eliding processor did not perform any external writeoperations to the lock, the hardware ensures program order of operationson the lock. If the eliding processor itself reads the value of the lockin the critical section, it will appear as if the processor had acquiredthe lock, i.e. the read will return the non-elided value. This behaviorallows an HLE execution to be functionally equivalent to an executionwithout the HLE prefixes.

An XRELEASE prefix can be added in front of an instruction that is usedto release the lock protecting a critical section. Releasing the lockinvolves a write to the lock. If the instruction is to restore the valueof the lock to the value the lock had prior to the XACQUIRE prefixedlock acquire operation on the same lock, then the processor elides theexternal write request associated with the release of the lock and doesnot add the address of the lock to the write-set. The processor thenattempts to commit the transactional execution.

With HLE, if multiple threads execute critical sections protected by thesame lock but they do not perform any conflicting operations on eachother's data, then the threads can execute concurrently and withoutserialization. Even though the software uses lock acquisition operationson a common lock, the hardware recognizes this, elides the lock, andexecutes the critical sections on the two threads without requiring anycommunication through the lock—if such communication was dynamicallyunnecessary.

If the processor is unable to execute the region transactionally, thenthe processor will execute the region non-transactionally and withoutelision. HLE enabled software has the same forward progress guaranteesas the underlying non-HLE lock-based execution. For successful HLEexecution, the lock and the critical section code must follow certainguidelines. These guidelines only affect performance; and failure tofollow these guidelines will not result in a functional failure.Hardware without HLE support will ignore the XACQUIRE and XRELEASEprefix hints and will not perform any elision since these prefixescorrespond to the REPNE/REPE IA-32 prefixes which are ignored on theinstructions where XACQUIRE and XRELEASE are valid. Importantly, HLE iscompatible with the existing lock-based programming model. Improper useof hints will not cause functional bugs though it may expose latent bugsalready in the code.

Restricted Transactional Memory (RTM) provides a flexible softwareinterface for transactional execution. RTM provides three newinstructions—XBEGIN, XEND, and XABORT—for programmers to start, commit,and abort a transactional execution.

The programmer uses the XBEGIN instruction to specify the start of atransactional code region and the XEND instruction to specify the end ofthe transactional code region. If the RTM region could not besuccessfully executed transactionally, then the XBEGIN instruction takesan operand that provides a relative offset to the fallback instructionaddress.

A processor may abort RTM transactional execution for many reasons. Inmany instances, the hardware automatically detects transactional abortconditions and restarts execution from the fallback instruction addresswith the architectural state corresponding to that present at the startof the XBEGIN instruction and the EAX register updated to describe theabort status.

The XABORT instruction allows programmers to abort the execution of anRTM region explicitly. The XABORT instruction takes an 8-bit immediateargument that is loaded into the EAX register and will thus be availableto software following an RTM abort. RTM instructions do not have anydata memory location associated with them. While the hardware providesno guarantees as to whether an RTM region will ever successfully committransactionally, most transactions that follow the recommendedguidelines are expected to successfully commit transactionally. However,programmers must always provide an alternative code sequence in thefallback path to guarantee forward progress. This may be as simple asacquiring a lock and executing the specified code regionnon-transactionally. Further, a transaction that always aborts on agiven implementation may complete transactionally on a futureimplementation. Therefore, programmers must ensure the code paths forthe transactional region and the alternative code sequence arefunctionally tested.

Detection of HLE Support

A processor supports HLE execution if CPUID.07H.EBX.HLE [bit 4]=1.However, an application can use the HLE prefixes (XACQUIRE and XRELEASE)without checking whether the processor supports HLE. Processors withoutHLE support ignore these prefixes and will execute the code withoutentering transactional execution.

Detection of RTM Support

A processor supports RTM execution if CPUID.07H.EBX.RTM [bit 11]=1. Anapplication must check if the processor supports RTM before it uses theRTM instructions (XBEGIN, XEND, XABORT). These instructions willgenerate a #UD exception when used on a processor that does not supportRTM.

Detection of XTEST Instruction

A processor supports the XTEST instruction if it supports either HLE orRTM. An application must check either of these feature flags beforeusing the XTEST instruction. This instruction will generate a #UDexception when used on a processor that does not support either HLE orRTM.

Querying Transactional Execution Status

The XTEST instruction can be used to determine the transactional statusof a transactional region specified by HLE or RTM. Note, while the HLEprefixes are ignored on processors that do not support HLE, the XTESTinstruction will generate a #UD exception when used on processors thatdo not support either HLE or RTM.

Requirements for HLE Locks

For HLE execution to successfully commit transactionally, the lock mustsatisfy certain properties and access to the lock must follow certainguidelines.

An XRELEASE prefixed instruction must restore the value of the elidedlock to the value it had before the lock acquisition. This allowshardware to safely elide locks by not adding them to the write-set. Thedata size and data address of the lock release (XRELEASE prefixed)instruction must match that of the lock acquire (XACQUIRE prefixed) andthe lock must not cross a cache line boundary.

Software should not write to the elided lock inside a transactional HLEregion with any instruction other than an XRELEASE prefixed instruction,otherwise such a write may cause a transactional abort. In addition,recursive locks (where a thread acquires the same lock multiple timeswithout first releasing the lock) may also cause a transactional abort.Note that software can observe the result of the elided lock acquireinside the critical section. Such a read operation will return the valueof the write to the lock.

The processor automatically detects violations to these guidelines, andsafely transitions to a non-transactional execution without elision.Since Intel TSX detects conflicts at the granularity of a cache line,writes to data collocated on the same cache line as the elided lock maybe detected as data conflicts by other logical processors eliding thesame lock.

Transactional Nesting

Both HLE and RTM support nested transactional regions. However, atransactional abort restores state to the operation that startedtransactional execution: either the outermost XACQUIRE prefixed HLEeligible instruction or the outermost XBEGIN instruction. The processortreats all nested transactions as one transaction.

HLE Nesting and Elision

Programmers can nest HLE regions up to an implementation specific depthof MAX_HLE_NEST_COUNT. Each logical processor tracks the nesting countinternally but this count is not available to software. An XACQUIREprefixed HLE-eligible instruction increments the nesting count, and anXRELEASE prefixed HLE-eligible instruction decrements it. The logicalprocessor enters transactional execution when the nesting count goesfrom zero to one. The logical processor attempts to commit only when thenesting count becomes zero. A transactional abort may occur if thenesting count exceeds MAX_HLE_NEST_COUNT.

In addition to supporting nested HLE regions, the processor can alsoelide multiple nested locks. The processor tracks a lock for elisionbeginning with the XACQUIRE prefixed HLE eligible instruction for thatlock and ending with the XRELEASE prefixed HLE eligible instruction forthat same lock. The processor can, at any one time, track up to aMAX_HLE_ELIDED_LOCKS number of locks. For example, if the implementationsupports a MAX_HLE_ELIDED_LOCKS value of two and if the programmer neststhree HLE identified critical sections (by performing XACQUIRE prefixedHLE eligible instructions on three distinct locks without performing anintervening XRELEASE prefixed HLE eligible instruction on any one of thelocks), then the first two locks will be elided, but the third won't beelided (but will be added to the transaction's writeset). However, theexecution will still continue transactionally. Once an XRELEASE for oneof the two elided locks is encountered, a subsequent lock acquiredthrough the XACQUIRE prefixed HLE eligible instruction will be elided.

The processor attempts to commit the HLE execution when all elidedXACQUIRE and XRELEASE pairs have been matched, the nesting count goes tozero, and the locks have satisfied requirements. If execution cannotcommit atomically, then execution transitions to a non-transactionalexecution without elision as if the first instruction did not have anXACQUIRE prefix.

RTM Nesting

Programmers can nest RTM regions up to an implementation specificMAX_RTM_NEST_COUNT. The logical processor tracks the nesting countinternally but this count is not available to software. An XBEGINinstruction increments the nesting count, and an XEND instructiondecrements the nesting count. The logical processor attempts to commitonly if the nesting count becomes zero. A transactional abort occurs ifthe nesting count exceeds MAX_RTM_NEST_COUNT.

Nesting HLE and RTM

HLE and RTM provide two alternative software interfaces to a commontransactional execution capability. Transactional processing behavior isimplementation specific when HLE and RTM are nested together, e.g., HLEis inside RTM or RTM is inside HLE. However, in all cases, theimplementation will maintain HLE and RTM semantics. An implementationmay choose to ignore HLE hints when used inside RTM regions, and maycause a transactional abort when RTM instructions are used inside HLEregions. In the latter case, the transition from transactional tonon-transactional execution occurs seamlessly since the processor willre-execute the HLE region without actually doing elision, and thenexecute the RTM instructions.

Abort Status Definition

RTM uses the EAX register to communicate abort status to software.Following an RTM abort the EAX register has the following definition.

TABLE 1 RTM Abort Status Definition EAX Register Bit Position Meaning 0Set if abort caused by XABORT instruction 1 If set, the transaction maysucceed on retry, this bit is always clear if bit 0 is set 2 Set ifanother logical processor conflicted with a memory address that was partof the transaction that aborted 3 Set if an internal buffer overflowed 4Set if a debug breakpoint was hit 5 Set if an abort occurred duringexecution of a nested transaction 23:6 Reserved 31-24 XABORT argument(only valid if bit 0 set, otherwise reserved)

The EAX abort status for RTM only provides causes for aborts. It doesnot by itself encode whether an abort or commit occurred for the RTMregion. The value of EAX can be 0 following an RTM abort. For example, aCPUID instruction when used inside an RTM region causes a transactionalabort and may not satisfy the requirements for setting any of the EAXbits. This may result in an EAX value of 0.

RTM Memory Ordering

A successful RTM commit causes all memory operations in the RTM regionto appear to execute atomically. A successfully committed RTM regionconsisting of an XBEGIN followed by an XEND, even with no memoryoperations in the RTM region, has the same ordering semantics as a LOCKprefixed instruction.

The XBEGIN instruction does not have fencing semantics. However, if anRTM execution aborts, then all memory updates from within the RTM regionare discarded and are not made visible to any other logical processor.

RTM-Enabled Debugger Support

By default, any debug exception inside an RTM region will cause atransactional abort and will redirect control flow to the fallbackinstruction address with architectural state recovered and bit 4 in EAXset. However, to allow software debuggers to intercept execution ondebug exceptions, the RTM architecture provides additional capability.

If bit 11 of DR7 and bit 15 of the IA32_DEBUGCTL_MSR are both 1, any RTMabort due to a debug exception (#DB) or breakpoint exception (#BP)causes execution to roll back and restart from the XBEGIN instructioninstead of the fallback address. In this scenario, the EAX register willalso be restored back to the point of the XBEGIN instruction.

Programming Considerations

Typical programmer-identified regions are expected to transactionallyexecute and commit successfully. However, Intel TSX does not provide anysuch guarantee. A transactional execution may abort for many reasons. Totake full advantage of the transactional capabilities, programmersshould follow certain guidelines to increase the probability of theirtransactional execution committing successfully.

This section discusses various events that may cause transactionalaborts. The architecture ensures that updates performed within atransaction that subsequently aborts execution will never becomevisible. Only committed transactional executions initiate an update tothe architectural state. Transactional aborts never cause functionalfailures and only affect performance.

Instruction Based Considerations

Programmers can use any instruction safely inside a transaction (HLE orRTM) and can use transactions at any privilege level. However, someinstructions will always abort the transactional execution and causeexecution to seamlessly and safely transition to a non-transactionalpath.

Intel TSX allows for most common instructions to be used insidetransactions without causing aborts. The following operations inside atransaction do not typically cause an abort:

-   -   Operations on the instruction pointer register, general purpose        registers (GPRs) and the status flags (CF, OF, SF, PF, AF, and        ZF); and    -   Operations on XMM and YMM registers and the MXCSR register.

However, programmers must be careful when intermixing SSE and AVXoperations inside a transactional region. Intermixing SSE instructionsaccessing XMM registers and AVX instructions accessing YMM registers maycause transactions to abort. Programmers may use REP/REPNE prefixedstring operations inside transactions. However, long strings may causeaborts. Further, the use of CLD and STD instructions may cause aborts ifthey change the value of the DF flag. However, if DF is 1, the STDinstruction will not cause an abort. Similarly, if DF is 0, then the CLDinstruction will not cause an abort.

Instructions not enumerated here as causing abort when used inside atransaction will typically not cause a transaction to abort (examplesinclude but are not limited to MFENCE, LFENCE, SFENCE, RDTSC, RDTSCP,etc.).

The following instructions will abort transactional execution on anyimplementation:

-   -   XABORT    -   CPUID    -   PAUSE

In addition, in some implementations, the following instructions mayalways cause transactional aborts. These instructions are not expectedto be commonly used inside typical transactional regions. However,programmers must not rely on these instructions to force a transactionalabort, since whether they cause transactional aborts is implementationdependent.

-   -   Operations on X87 and MMX architecture state. This includes all        MMX and X87 instructions, including the FXRSTOR and FXSAVE        instructions.    -   Update to non-status portion of EFLAGS: CLI, STI, POPFD, POPFQ,        CLTS.    -   Instructions that update segment registers, debug registers        and/or control registers: MOV to DS/ES/FS/GS/SS, POP        DS/ES/FS/GS/SS, LDS, LES, LFS, LGS, LSS, SWAPGS, WRFSBASE,        WRGSBASE, LGDT, SGDT, LIDT, SIDT, LLDT, SLDT, LTR, STR, Far        CALL, Far JMP, Far RET, IRET, MOV to DRx, MOV to        CR0/CR2/CR3/CR4/CR8 and LMSW.    -   Ring transitions: SYSENTER, SYSCALL, SYSEXIT, and SYSRET.    -   TLB and Cacheability control: CLFLUSH, INVD, WBINVD, INVLPG,        INVPCID, and memory instructions with a non-temporal hint        (MOVNTDQA, MOVNTDQ, MOVNTI, MOVNTPD, MOVNTPS, and MOVNTQ).    -   Processor state save: XSAVE, XSAVEOPT, and XRSTOR.    -   Interrupts: INTn, INTO.    -   IO: IN, INS, REP INS, OUT, OUTS, REP OUTS and their variants.    -   VMX: VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL,        VMLAUNCH, VMRESUME, VMXOFF, VMXON, INVEPT, and INVVPID.    -   SMX: GETSEC.    -   UD2, RSM, RDMSR, WRMSR, HLT, MONITOR, MWAIT, XSETBV, VZEROUPPER,        MASKMOVQ, and V/MASKMOVDQU.        Runtime Considerations

In addition to the instruction-based considerations, runtime events maycause transactional execution to abort. These may be due to data accesspatterns or micro-architectural implementation features. The followinglist is not a comprehensive discussion of all abort causes.

Any fault or trap in a transaction that must be exposed to software willbe suppressed. Transactional execution will abort and execution willtransition to a non-transactional execution, as if the fault or trap hadnever occurred. If an exception is not masked, then that un-maskedexception will result in a transactional abort and the state will appearas if the exception had never occurred.

Synchronous exception events (#DE, #OF, #NP, #SS, #GP, #BR, #UD, #AC,#XF, #PF, #NM, #TS, #MF, #DB, #BP/INT3) that occur during transactionalexecution may cause an execution not to commit transactionally, andrequire a non-transactional execution. These events are suppressed as ifthey had never occurred. With HLE, since the non-transactional code pathis identical to the transactional code path, these events will typicallyre-appear when the instruction that caused the exception is re-executednon-transactionally, causing the associated synchronous events to bedelivered appropriately in the non-transactional execution. Asynchronousevents (NMI, SMI, INTR, IPI, PMI, etc.) occurring during transactionalexecution may cause the transactional execution to abort and transitionto a non-transactional execution. The asynchronous events will be pendedand handled after the transactional abort is processed.

Transactions only support write-back cacheable memory type operations. Atransaction may always abort if the transaction includes operations onany other memory type. This includes instruction fetches to UC memorytype.

Memory accesses within a transactional region may require the processorto set the Accessed and Dirty flags of the referenced page table entry.The behavior of how the processor handles this is implementationspecific. Some implementations may allow the updates to these flags tobecome externally visible even if the transactional region subsequentlyaborts. Some Intel TSX implementations may choose to abort thetransactional execution if these flags need to be updated. Further, aprocessor's page-table walk may generate accesses to its owntransactionally written but uncommitted state. Some Intel TSXimplementations may choose to abort the execution of a transactionalregion in such situations. Regardless, the architecture ensures that, ifthe transactional region aborts, then the transactionally written statewill not be made architecturally visible through the behavior ofstructures such as TLBs.

Executing self-modifying code transactionally may also causetransactional aborts. Programmers must continue to follow the Intelrecommended guidelines for writing self-modifying and cross-modifyingcode even when employing HLE and RTM. While an implementation of RTM andHLE will typically provide sufficient resources for executing commontransactional regions, implementation constraints and excessive sizesfor transactional regions may cause a transactional execution to abortand transition to a non-transactional execution. The architectureprovides no guarantee of the amount of resources available to dotransactional execution and does not guarantee that a transactionalexecution will ever succeed.

Conflicting requests to a cache line accessed within a transactionalregion may prevent the transaction from executing successfully. Forexample, if logical processor P0 reads line A in a transactional regionand another logical processor P1 writes line A (either inside or outsidea transactional region) then logical processor P0 may abort if logicalprocessor P1's write interferes with processor P0's ability to executetransactionally.

Similarly, if P0 writes line A in a transactional region and P1 reads orwrites line A (either inside or outside a transactional region), then P0may abort if P1's access to line A interferes with P0's ability toexecute transactionally. In addition, other coherence traffic may attimes appear as conflicting requests and may cause aborts. While thesefalse conflicts may happen, they are expected to be uncommon. Theconflict resolution policy to determine whether P0 or P1 aborts in theabove scenarios is implementation specific.

Generic Transaction Execution Embodiments:

According to “ARCHITECTURES FOR TRANSACTIONAL MEMORY”, a dissertationsubmitted to the Department of Computer Science and the Committee onGraduate Studies of Stanford University in partial fulfillment of therequirements for the Degree of Doctor of Philosophy, by Austen McDonald,June 2009, incorporated by reference herein in its entirety,fundamentally, there are three mechanisms needed to implement an atomicand isolated transactional region: versioning, conflict detection, andcontention management.

To make a transactional code region appear atomic, all the modificationsperformed by that transactional code region must be stored and keptisolated from other transactions until commit time. The system does thisby implementing a versioning policy. Two versioning paradigms exist:eager and lazy. An eager versioning system stores newly generatedtransactional values in place and stores previous memory values on theside, in what is called an undo-log. A lazy versioning system stores newvalues temporarily in what is called a write buffer, copying them tomemory only on commit. In either system, the cache is used to optimizestorage of new versions.

To ensure that transactions appear to be performed atomically, conflictsmust be detected and resolved. The two systems, i.e., the eager and lazyversioning systems, detect conflicts by implementing a conflictdetection policy, either optimistic or pessimistic. An optimistic systemexecutes transactions in parallel, checking for conflicts only when atransaction commits. A pessimistic system checks for conflicts at eachload and store. Similar to versioning, conflict detection also uses thecache, marking each line as either part of the read-set, part of thewrite-set, or both. The two systems resolve conflicts by implementing acontention management policy. Many contention management policies exist,some are more appropriate for optimistic conflict detection and some aremore appropriate for pessimistic. Described below are some examplepolicies.

Since each transactional memory (TM) system needs both versioningdetection and conflict detection, these options give rise to fourdistinct TM designs: Eager-Pessimistic (EP), Eager-Optimistic (EO),Lazy-Pessimistic (LP), and Lazy-Optimistic (LO). Table 2 brieflydescribes all four distinct TM designs.

FIGS. 1 and 2 depict an example of a multicore TM environment. FIG. 1shows many TM-enabled CPUs (CPU1 114 a, CPU2 114 b, etc.) on one die100, connected with an interconnect 122, under management of aninterconnect control 120 a, 120 b. Each CPU 114 a, 114 b (also known asa Processor) may have a split cache consisting of an Instruction Cache116 a, 116 b for caching instructions from memory to be executed and aData Cache 118 a, 118 b with TM support for caching data (operands) ofmemory locations to be operated on by CPU 114 a, 114 b (in FIG. 1, eachCPU 114 a, 114 b and its associated caches are referenced as 112 a, 112b). In an implementation, caches of multiple dies 100 are interconnectedto support cache coherency between the caches of the multiple dies 100.In an implementation, a single cache, rather than the split cache isemployed holding both instructions and data. In implementations, the CPUcaches are one level of caching in a hierarchical cache structure. Forexample each die 100 may employ a shared cache 124 to be shared amongstall the CPUs on the die 100. In another implementation, each die mayhave access to a shared cache 124, shared amongst all the processors ofall the dies 100.

FIG. 2 shows the details of an example transactional CPU environment112, having a CPU 114, including additions to support TM. Thetransactional CPU (processor) 114 may include hardware for supportingRegister Checkpoints 126 and special TM Registers 128. The transactionalCPU cache may have the MESI bits 130, Tags 140 and Data 142 of aconventional cache but also, for example, R bits 132 showing a line hasbeen read by the CPU 114 while executing a transaction and W bits 138showing a line has been written-to by the CPU 114 while executing atransaction.

A key detail for programmers in any TM system is how non-transactionalaccesses interact with transactions. By design, transactional accessesare screened from each other using the mechanisms above. However, theinteraction between a regular, non-transactional load with a transactioncontaining a new value for that address must still be considered. Inaddition, the interaction between a non-transactional store with atransaction that has read that address must also be explored. These areissues of the database concept isolation.

A TM system is said to implement strong isolation, sometimes calledstrong atomicity, when every non-transactional load and store acts likean atomic transaction. Therefore, non-transactional loads cannot seeuncommitted data and non-transactional stores cause atomicity violationsin any transactions that have read that address. A system where this isnot the case is said to implement weak isolation, sometimes called weakatomicity.

Strong isolation is often more desirable than weak isolation due to therelative ease of conceptualization and implementation of strongisolation. Additionally, if a programmer has forgotten to surround someshared memory references with transactions, causing bugs, then withstrong isolation, the programmer will often detect that oversight usinga simple debug interface because the programmer will see anon-transactional region causing atomicity violations. Also, programswritten in one model may work differently on another model.

Further, strong isolation is often easier to support in hardware TM thanweak isolation. With strong isolation, since the coherence protocolalready manages load and store communication between processors,transactions can detect non-transactional loads and stores and actappropriately. To implement strong isolation in software TransactionalMemory (TM), non-transactional code must be modified to include read-and write-barriers; potentially crippling performance. Although greateffort has been expended to remove many un-needed barriers, suchtechniques are often complex and performance is typically far lower thanthat of HTMs.

TABLE 2 Transactional Memory Design Space VERSIONING Lazy Eager CONFLICTOptimistic Storing updates in a write Not practical: waiting to updateDETECTION buffer; detecting conflicts at memory until commit time butcommit time. detecting conflicts at access time guarantees wasted workand provides no advantage Pessimistic Storing updates in a writeUpdating memory, keeping old buffer; detecting conflicts at values inundo log; detecting access time. conflicts at access time.

Table 2 illustrates the fundamental design space of transactional memory(versioning and conflict detection).

Eager-Pessimistic (EP)

This first TM design described below is known as Eager-Pessimistic. AnEP system stores its write-set “in place” (hence the name “eager”) and,to support rollback, stores the old values of overwritten lines in an“undo log”. Processors use the W 138 and R 132 cache bits to track readand write-sets and detect conflicts when receiving snooped loadrequests. Perhaps the most notable examples of EP systems in knownliterature are LogTM and UTM.

Beginning a transaction in an EP system is much like beginning atransaction in other systems: tm_begin( ) takes a register checkpoint,and initializes any status registers. An EP system also requiresinitializing the undo log, the details of which are dependent on the logformat, but often involve initializing a log base pointer to a region ofpre-allocated, thread-private memory, and clearing a log boundsregister.

Versioning: In EP, due to the way eager versioning is designed tofunction, the MESI 130 state transitions (cache line indicatorscorresponding to Modified, Exclusive, Shared, and Invalid code states)are left mostly unchanged. Outside of a transaction, the MESI 130 statetransitions are left completely unchanged. When reading a line inside atransaction, the standard coherence transitions apply (S (Shared)→S, I(Invalid)→S, or I→E (Exclusive)), issuing a load miss as needed, but theR 132 bit is also set. Likewise, writing a line applies the standardtransitions (S→M, E→I, I→M), issuing a miss as needed, but also sets theW 138 (Written) bit. The first time a line is written, the old versionof the entire line is loaded then written to the undo log to preserve itin case the current transaction aborts. The newly written data is thenstored “in-place,” over the old data.

Conflict Detection: Pessimistic conflict detection uses coherencemessages exchanged on misses, or upgrades, to look for conflicts betweentransactions. When a read miss occurs within a transaction, otherprocessors receive a load request; but they ignore the request if theydo not have the needed line. If the other processors have the neededline non-speculatively or have the line R 132 (Read), they downgradethat line to S, and in certain cases issue a cache-to-cache transfer ifthey have the line in MESI's 130 M or E state. However, if the cache hasthe line W 138, then a conflict is detected between the two transactionsand additional action(s) must be taken.

Similarly, when a transaction seeks to upgrade a line from shared tomodified (on a first write), the transaction issues an exclusive loadrequest, which is also used to detect conflicts. If a receiving cachehas the line non-speculatively, then the line is invalidated, and incertain cases a cache-to-cache transfer (M or E states) is issued. But,if the line is R 132 or W 138, a conflict is detected.

Validation: Because conflict detection is performed on every load, atransaction always has exclusive access to its own write-set. Therefore,validation does not require any additional work.

Commit: Since eager versioning stores the new version of data items inplace, the commit process simply clears the W 138 and R 132 bits anddiscards the undo log.

Abort: When a transaction rolls back, the original version of each cacheline in the undo log must be restored, a process called “unrolling” or“applying” the log. This is done during tm_discard( ) and must be atomicwith regard to other transactions. Specifically, the write-set muststill be used to detect conflicts: this transaction has the only correctversion of lines in its undo log, and requesting transactions must waitfor the correct version to be restored from that log. Such a log can beapplied using a hardware state machine or software abort handler.

Eager-Pessimistic has the characteristics of: Commit is simple and sinceit is in-place, very fast. Similarly, validation is a no-op. Pessimisticconflict detection detects conflicts early, thereby reducing the numberof “doomed” transactions. For example, if two transactions are involvedin a Write-After-Read dependency, then that dependency is detectedimmediately in pessimistic conflict detection. However, in optimisticconflict detection such conflicts are not detected until the writercommits.

Eager-Pessimistic also has the characteristics of: As described above,the first time a cache line is written, the old value must be written tothe log, incurring extra cache accesses. Aborts are expensive as theyrequire undoing the log. For each cache line in the log, a load must beissued, perhaps going as far as main memory before continuing to thenext line. Pessimistic conflict detection also prevents certainserializable schedules from existing.

Additionally, because conflicts are handled as they occur, there is apotential for livelock and careful contention management mechanisms mustbe employed to guarantee forward progress.

Lazy-Optimistic (LO)

Another popular TM design is Lazy-Optimistic (LO), which stores itswrite-set in a “write buffer” or “redo log” and detects conflicts atcommit time (still using the R 132 and W 138 bits).

Versioning: Just as in the EP system, the MESI protocol of the LO designis enforced outside of the transactions. Once inside a transaction,reading a line incurs the standard MESI transitions but also sets the R132 bit. Likewise, writing a line sets the W 138 bit of the line, buthandling the MESI transitions of the LO design is different from that ofthe EP design. First, with lazy versioning, the new versions of writtendata are stored in the cache hierarchy until commit while othertransactions have access to old versions available in memory or othercaches. To make available the old versions, dirty lines (M lines) mustbe evicted when first written by a transaction. Second, no upgrademisses are needed because of the optimistic conflict detection feature:if a transaction has a line in the S state, it can simply write to itand upgrade that line to an M state without communicating the changeswith other transactions because conflict detection is done at committime.

Conflict Detection and Validation: To validate a transaction and detectconflicts, LO communicates the addresses of speculatively modified linesto other transactions only when it is preparing to commit. Onvalidation, the processor sends one, potentially large, network packetcontaining all the addresses in the write-set. Data is not sent, butleft in the cache of the committer and marked dirty (M). To build thispacket without searching the cache for lines marked W, a simple bitvector is used, called a “store buffer,” with one bit per cache line totrack these speculatively modified lines. Other transactions use thisaddress packet to detect conflicts: if an address is found in the cacheand the R 132 and/or W 138 bits are set, then a conflict is initiated.If the line is found but neither R 132 nor W 138 is set, then the lineis simply invalidated, which is similar to processing an exclusive load.

To support transaction atomicity, these address packets must be handledatomically, i.e., no two address packets may exist at once with the sameaddresses. In an LO system, this can be achieved by simply acquiring aglobal commit token before sending the address packet. However, atwo-phase commit scheme could be employed by first sending out theaddress packet, collecting responses, enforcing an ordering protocol(perhaps oldest transaction first), and committing once all responsesare satisfactory.

Commit: Once validation has occurred, commit needs no special treatment:simply clear W 138 and R 132 bits and the store buffer. Thetransaction's writes are already marked dirty in the cache and othercaches' copies of these lines have been invalidated via the addresspacket. Other processors can then access the committed data through theregular coherence protocol.

Abort: Rollback is equally easy: because the write-set is containedwithin the local caches, these lines can be invalidated, then clear W138 and R 132 bits and the store buffer. The store buffer allows W linesto be found to invalidate without the need to search the cache.

Lazy-Optimistic has the characteristics of: Aborts are very fast,requiring no additional loads or stores and making only local changes.More serializable schedules can exist than found in EP, which allows anLO system to more aggressively speculate that transactions areindependent, which can yield higher performance. Finally, the latedetection of conflicts can increase the likelihood of forward progress.

Lazy-Optimistic also has the characteristics of: Validation takes globalcommunication time proportional to size of write set. Doomedtransactions can waste work since conflicts are detected only at committime.

Lazy-Pessimistic (LP)

Lazy-Pessimistic (LP) represents a third TM design option, sittingsomewhere between EP and LO: storing newly written lines in a writebuffer but detecting conflicts on a per access basis.

Versioning: Versioning is similar but not identical to that of LO:reading a line sets its R bit 132, writing a line sets its W bit 138,and a store buffer is used to track W lines in the cache. Also, dirty(M) lines must be evicted when first written by a transaction, just asin LO. However, since conflict detection is pessimistic, load exclusivesmust be performed when upgrading a transactional line from I, S→M, whichis unlike LO.

Conflict Detection: LP's conflict detection operates the same as EP's:using coherence messages to look for conflicts between transactions.

Validation: Like in EP, pessimistic conflict detection ensures that atany point, a running transaction has no conflicts with any other runningtransaction, so validation is a no-op.

Commit: Commit needs no special treatment: simply clear W 138 and R 132bits and the store buffer, like in LO.

Abort: Rollback is also like that of LO: simply invalidate the write-setusing the store buffer and clear the W and R bits and the store buffer.

Eager-Optimistic (EO)

The LP has the characteristics of: Like LO, aborts are very fast. LikeEP, the use of pessimistic conflict detection reduces the number of“doomed” transactions Like EP, some serializable schedules are notallowed and conflict detection must be performed on each cache miss.

The final combination of versioning and conflict detection isEager-Optimistic (EO). EO may be a less than optimal choice for HTMsystems: since new transactional versions are written in-place, othertransactions have no choice but to notice conflicts as they occur (i.e.,as cache misses occur). But since EO waits until commit time to detectconflicts, those transactions become “zombies,” continuing to execute,wasting resources, yet are “doomed” to abort.

EO has proven to be useful in STMs and is implemented by Bartok-STM andMcRT. A lazy versioning STM needs to check its write buffer on each readto ensure that it is reading the most recent value. Since the writebuffer is not a hardware structure, this is expensive, hence thepreference for write-in-place eager versioning. Additionally, sincechecking for conflicts is also expensive in an STM, optimistic conflictdetection offers the advantage of performing this operation in bulk.

Contention Management

How a transaction rolls back once the system has decided to abort thattransaction has been described above, but, since a conflict involves twotransactions, the topics of which transaction should abort, how thatabort should be initiated, and when should the aborted transaction beretried need to be explored. These are topics that are addressed byContention Management (CM), a key component of transactional memory.Described below are policies regarding how the systems initiate abortsand the various established methods of managing which transactionsshould abort in a conflict.

Contention Management Policies

A Contention Management (CM) Policy is a mechanism that determines whichtransaction involved in a conflict should abort and when the abortedtransaction should be retried. For example, it is often the case thatretrying an aborted transaction immediately does not lead to the bestperformance. Conversely, employing a back-off mechanism, which delaysthe retrying of an aborted transaction, can yield better performance.STMs first grappled with finding the best contention management policiesand many of the policies outlined below were originally developed forSTMs.

CM Policies draw on a number of measures to make decisions, includingages of the transactions, size of read- and write-sets, the number ofprevious aborts, etc. The combinations of measures to make suchdecisions are endless, but certain combinations are described below,roughly in order of increasing complexity.

To establish some nomenclature, first note that in a conflict there aretwo sides: the attacker and the defender. The attacker is thetransaction requesting access to a shared memory location. Inpessimistic conflict detection, the attacker is the transaction issuingthe load or load exclusive. In optimistic, the attacker is thetransaction attempting to validate. The defender in both cases is thetransaction receiving the attacker's request.

An Aggressive CM Policy immediately and always retries either theattacker or the defender. In LO, Aggressive means that the attackeralways wins, and so Aggressive is sometimes called committer wins. Sucha policy was used for the earliest LO systems. In the case of EP,Aggressive can be either defender wins or attacker wins.

Restarting a conflicting transaction that will immediately experienceanother conflict is bound to waste work—namely interconnect bandwidthrefilling cache misses. A Polite CM Policy employs exponential backoff(but linear could also be used) before restarting conflicts. To preventstarvation, a situation where a process does not have resourcesallocated to it by the scheduler, the exponential backoff greatlyincreases the odds of transaction success after some n retries.

Another approach to conflict resolution is to randomly abort theattacker or defender (a policy called Randomized). Such a policy may becombined with a randomized backoff scheme to avoid unneeded contention.

However, making random choices, when selecting a transaction to abort,can result in aborting transactions that have completed “a lot of work”,which can waste resources. To avoid such waste, the amount of workcompleted on the transaction can be taken into account when determiningwhich transaction to abort. One measure of work could be a transaction'sage. Other methods include Oldest, Bulk TM, Size Matters, Karma, andPolka. Oldest is a simple timestamp method that aborts the youngertransaction in a conflict. Bulk TM uses this scheme. Size Matters islike Oldest but instead of transaction age, the number of read/writtenwords is used as the priority, reverting to Oldest after a fixed numberof aborts. Karma is similar, using the size of the write-set aspriority. Rollback then proceeds after backing off a fixed amount oftime. Aborted transactions keep their priorities after being aborted(hence the name Karma). Polka works like Karma but instead of backingoff a predefined amount of time, it backs off exponentially more eachtime.

Since aborting wastes work, it is logical to argue that stalling anattacker until the defender has finished their transaction would lead tobetter performance. Unfortunately, such a simple scheme easily leads todeadlock.

Deadlock avoidance techniques can be used to solve this problem. Greedyuses two rules to avoid deadlock. The first rule is, if a firsttransaction, T1, has lower priority than a second transaction, T0, or ifT1 is waiting for another transaction, then T1 aborts when conflictingwith T0. The second rule is, if T1 has higher priority than T0 and isnot waiting, then T0 waits until T1 commits, aborts, or starts waiting(in which case the first rule is applied). Greedy provides someguarantees about time bounds for executing a set of transactions. One EPdesign (LogTM) uses a CM policy similar to Greedy to achieve stallingwith conservative deadlock avoidance.

Example MESI coherency rules provide for four possible states in which acache line of a multiprocessor cache system may reside, M, E, S, and I,defined as follows:

Modified (M): The cache line is present only in the current cache, andis dirty; it has been modified from the value in main memory. The cacheis required to write the data back to main memory at some time in thefuture, before permitting any other read of the (no longer valid) mainmemory state. The write-back changes the line to the Exclusive state.

Exclusive (E): The cache line is present only in the current cache, butis clean; it matches main memory. It may be changed to the Shared stateat any time, in response to a read request. Alternatively, it may bechanged to the Modified state when writing to it.

Shared (S): Indicates that this cache line may be stored in other cachesof the machine and is “clean”; it matches the main memory. The line maybe discarded (changed to the Invalid state) at any time.

Invalid (I): Indicates that this cache line is invalid (unused).

TM coherency status indicators (R 132, W 138) may be provided for eachcache line, in addition to, or encoded in the MESI coherency bits. An R132 indicator indicates the current transaction has read from the dataof the cache line, and a W 138 indicator indicates the currenttransaction has written to the data of the cache line.

In another aspect of TM design, a system is designed using transactionalstore buffers. U.S. Pat. No. 6,349,361 titled “Methods and Apparatus forReordering and Renaming Memory References in a Multiprocessor ComputerSystem,” filed Mar. 31, 2000 and incorporated by reference herein in itsentirety, teaches a method for reordering and renaming memory referencesin a multiprocessor computer system having at least a first and a secondprocessor. The first processor has a first private cache and a firstbuffer, and the second processor has a second private cache and a secondbuffer. The method includes the steps of, for each of a plurality ofgated store requests received by the first processor to store a datum,exclusively acquiring a cache line that contains the datum by the firstprivate cache, and storing the datum in the first buffer. Upon the firstbuffer receiving a load request from the first processor to load aparticular datum, the particular datum is provided to the firstprocessor from among the data stored in the first buffer based on anin-order sequence of load and store operations. Upon the first cachereceiving a load request from the second cache for a given datum, anerror condition is indicated and a current state of at least one of theprocessors is reset to an earlier state when the load request for thegiven datum corresponds to the data stored in the first buffer.

The main implementation components of one such transactional memoryfacility are a transaction-backup register file for holdingpre-transaction GR (general register) content, a cache directory totrack the cache lines accessed during the transaction, a store cache tobuffer stores until the transaction ends, and firmware routines toperform various complex functions. In this section a detailedimplementation is described.

IBM zEnterprise EC12 Enterprise Server Embodiment

The IBM zEnterprise EC12 enterprise server introduces transactionalexecution (TX) in transactional memory, and is described in part in apaper, “Transactional Memory Architecture and Implementation for IBMSystem z” of Proceedings Pages 25-36 presented at MICRO-45, 1-5 Dec.2012, Vancouver, British Columbia, Canada, available from IEEE ComputerSociety Conference Publishing Services (CPS), which is incorporated byreference herein in its entirety.

Table 3 shows an example transaction. Transactions started with TBEGINare not assured to ever successfully complete with TEND, since they canexperience an aborting condition at every attempted execution, e.g., dueto repeating conflicts with other CPUs. This requires that the programsupport a fallback path to perform the same operationnon-transactionally, e.g., by using traditional locking schemes. Thisputs a significant burden on the programming and software verificationteams, especially where the fallback path is not automatically generatedby a reliable compiler.

TABLE 3 Example Transaction Code LHI R0,0 *initialize retry count=0 loopTBEGIN *begin transaction JNZ abort *go to abort code if CC1=0 LT R1,lock *load and test the fallback lock JNZ lckbzy *branch if lock busy .. . perform operation . . . TEND *end transaction . . . . . . . . . . .. lckbzy TABORT *abort if lock busy; this *resumes after TBEGIN abort JOfallback *no retry if CC=3 AHI R0, 1 *increment retry count CIJNL R0,6,*give up after 6 attempts fallback PPA R0, TX *random delay based onretry count . . . potentially wait for lock to become free . . . J loop*jump back to retry fallback OBTAIN lock *using Compare&Swap . . .perform operation . . . RELEASE lock . . . . . . . . . . . .

The requirement of providing a fallback path for aborted TransactionExecution (TX) transactions can be onerous. Many transactions operatingon shared data structures are expected to be short, touch only a fewdistinct memory locations, and use simple instructions only. For thosetransactions, the IBM zEnterprise EC12 introduces the concept ofconstrained transactions; under normal conditions, the CPU 114 (FIG. 2)assures that constrained transactions eventually end successfully,albeit without giving a strict limit on the number of necessary retries.A constrained transaction starts with a TBEGINC instruction and endswith a regular TEND. Implementing a task as a constrained ornon-constrained transaction typically results in very comparableperformance, but constrained transactions simplify software developmentby removing the need for a fallback path. IBM's Transactional Executionarchitecture is further described in z/Architecture, Principles ofOperation, Tenth Edition, SA22-7832-09 published September 2012 fromIBM, incorporated by reference herein in its entirety.

A constrained transaction starts with the TBEGINC instruction. Atransaction initiated with TBEGINC must follow a list of programmingconstraints; otherwise the program takes a non-filterableconstraint-violation interruption. Exemplary constraints may include,but not be limited to: the transaction can execute a maximum of 32instructions, all instruction text must be within 256 consecutive bytesof memory; the transaction contains only forward-pointing relativebranches (i.e., no loops or subroutine calls); the transaction canaccess a maximum of 4 aligned octowords (an octoword is 32 bytes) ofmemory; and restriction of the instruction-set to exclude complexinstructions like decimal or floating-point operations. The constraintsare chosen such that many common operations like doubly linkedlist-insert/delete operations can be performed, including the verypowerful concept of atomic compare-and-swap targeting up to 4 alignedoctowords. At the same time, the constraints were chosen conservativelysuch that future CPU implementations can assure transaction successwithout needing to adjust the constraints, since that would otherwiselead to software incompatibility.

TBEGINC mostly behaves like XBEGIN in TSX or TBEGIN on IBM's zEC12servers, except that the floating-point register (FPR) control and theprogram interruption filtering fields do not exist and the controls areconsidered to be zero. On a transaction abort, the instruction addressis set back directly to the TBEGINC instead of to the instruction after,reflecting the immediate retry and absence of an abort path forconstrained transactions.

Nested transactions are not allowed within constrained transactions, butif a TBEGINC occurs within a non-constrained transaction it is treatedas opening a new non-constrained nesting level just like TBEGIN would.This can occur, e.g., if a non-constrained transaction calls asubroutine that uses a constrained transaction internally.

Since interruption filtering is implicitly off, all exceptions during aconstrained transaction lead to an interruption into the operatingsystem (OS). Eventual successful finishing of the transaction relies onthe capability of the OS to page-in the at most 4 pages touched by anyconstrained transaction. The OS must also ensure time-slices long enoughto allow the transaction to complete.

TABLE 4 Transaction Code Example TBEGINC *begin constrained transaction. . . perform operation . . . TEND *end transaction

Table 4 shows the constrained-transactional implementation of the codein Table 3, assuming that the constrained transactions do not interactwith other locking-based code. No lock testing is shown therefore, butcould be added if constrained transactions and lock-based code weremixed.

When failure occurs repeatedly, software emulation is performed usingmillicode as part of system firmware. Advantageously, constrainedtransactions have desirable properties because of the burden removedfrom programmers.

With reference to FIG. 3, the IBM zEnterprise EC12 processor introducedthe transactional execution facility. The processor can decode 3instructions per clock cycle; simple instructions are dispatched assingle micro-ops, and more complex instructions are cracked intomultiple micro-ops. The micro-ops (Uops 232 b) are written into aunified issue queue 216, from where they can be issued out-of-order. Upto two fixed-point, one floating-point, two load/store, and two branchinstructions can execute every cycle. A Global Completion Table (GCT)232 holds every micro-op 232 b and a transaction nesting depth (TND) 232a. The GCT 232 is written in-order at decode time, tracks the executionstatus of each micro-op 232 b, and completes instructions when allmicro-ops 232 b of the oldest instruction group have successfullyexecuted.

The level 1 (L1) data cache 240 is a 96 KB (kilo-byte) 6-way associativecache with 256 byte cache-lines and 4 cycle use latency, coupled to aprivate 1 MB (mega-byte) 8-way associative 2nd-level (L2) data cache 268with 7 cycles use-latency penalty for L1 240 misses. The L1 240 cache isthe cache closest to a processor and Ln cache is a cache at the nthlevel of caching. Both L1 240 and L2 268 caches are store-through. Sixcores on each central processor (CP) chip share a 48 MB 3rd-levelstore-in cache, and six CP chips are connected to an off-chip 384 MB4th-level cache, packaged together on a glass ceramic multi-chip module(MCM). Up to 4 multi-chip modules (MCMs) can be connected to a coherentsymmetric multi-processor (SMP) system with up to 144 cores (not allcores are available to run customer workload).

Coherency is managed with a variant of the MESI protocol. Cache-linescan be owned read-only (shared) or exclusive; the L1 240 and L2 268 arestore-through and thus do not contain dirty lines. The L3 272 and L4caches (not shown) are store-in and track dirty states. Each cache isinclusive of all its connected lower level caches.

Coherency requests are called “cross interrogates” (XI) and are senthierarchically from higher level to lower-level caches, and between theL4s. When one core misses the L1 240 and L2 268 and requests the cacheline from its local L3 272, the L3 272 checks whether it owns the line,and if necessary sends an XI to the currently owning L2 268/L1 240 underthat L3 272 to ensure coherency, before it returns the cache line to therequestor. If the request also misses the L3 272, the L3 272 sends arequest to the L4 (not shown), which enforces coherency by sending XIsto all necessary L3s under that L4, and to the neighboring L4s. Then theL4 responds to the requesting L3 which forwards the response to the L2268/L1 240.

Note that due to the inclusivity rule of the cache hierarchy, sometimescache lines are XI′ed from lower-level caches due to evictions onhigher-level caches caused by associativity overflows from requests toother cache lines. These XIs can be called “LRU XIs”, where LRU standsfor least recently used.

Making reference to yet another type of XI requests, Demote-XIstransition cache-ownership from exclusive into read-only state, andExclusive-XIs transition cache ownership from exclusive into invalidstate. Demote-XIs and Exclusive-XIs need a response back to the XIsender. The target cache can “accept” the XI, or send a “reject”response if it first needs to evict dirty data before accepting the XI.The L1 240/L2 268 caches are store through, but may reject demote-XIsand exclusive XIs if they have stores in their store queues that need tobe sent to L3 before downgrading the exclusive state. A rejected XI willbe repeated by the sender. Read-only-XIs are sent to caches that own theline read-only; no response is needed for such XIs since they cannot berejected. The details of the SMP protocol are similar to those describedfor the IBM z10 by P. Mak, C. Walters, and G. Strait, in “IBM System z10processor cache subsystem microarchitecture”, IBM Journal of Researchand Development, Vol 53:1, 2009, which is incorporated by referenceherein in its entirety.

Transactional Instruction Execution

FIG. 3 depicts example components of an example transactional executionenvironment, including a CPU and caches/components with which itinteracts (such as those depicted in FIGS. 1 and 2). The instructiondecode unit 208 (IDU) keeps track of the current transaction nestingdepth 212 (TND). When the IDU 208 receives a TBEGIN instruction, thenesting depth 212 is incremented, and conversely decremented on TENDinstructions. The nesting depth 212 is written into the GCT 232 forevery dispatched instruction. When a TBEGIN or TEND is decoded on aspeculative path that later gets flushed, the IDU's 208 nesting depth212 is refreshed from the youngest GCT 232 entry that is not flushed.The transactional state is also written into the issue queue 216 forconsumption by the execution units, mostly by the Load/Store Unit (LSU)280, which also has an effective address calculator 236 included in theLSU 280. The TBEGIN instruction may specify a transaction diagnosticblock (TDB) for recording status information, should the transactionabort before reaching a TEND instruction.

Similar to the nesting depth, the IDU 208/GCT 232 collaboratively trackthe access register/floating-point register (AR/FPR) modification masksthrough the transaction nest; the IDU 208 can place an abort requestinto the GCT 232 when an AR/FPR-modifying instruction is decoded and themodification mask blocks that. When the instruction becomesnext-to-complete, completion is blocked and the transaction aborts.Other restricted instructions are handled similarly, including TBEGIN ifdecoded while in a constrained transaction, or exceeding the maximumnesting depth.

An outermost TBEGIN is cracked into multiple micro-ops depending on theGR-Save-Mask; each micro-op 232 b (including, for example uop 0, uop 1,and uop2) will be executed by one of the two fixed point units (FXUs)220 to save a pair of GRs 228 into a special transaction-backup registerfile 224, that is used to later restore the GR 228 content in case of atransaction abort. Also the TBEGIN spawns micro-ops 232 b to perform anaccessibility test for the TDB if one is specified; the address is savedin a special purpose register for later usage in the abort case. At thedecoding of an outermost TBEGIN, the instruction address and theinstruction text of the TBEGIN are also saved in special purposeregisters for a potential abort processing later on.

TEND and NTSTG are single micro-op 232 b instructions; NTSTG(non-transactional store) is handled like a normal store except that itis marked as non-transactional in the issue queue 216 so that the LSU280 can treat it appropriately. TEND is a no-op at execution time, theending of the transaction is performed when TEND completes.

As mentioned, instructions that are within a transaction are marked assuch in the issue queue 216, but otherwise execute mostly unchanged; theLSU 280 performs isolation tracking as described in the next section.

Since decoding is in-order, and since the IDU 208 keeps track of thecurrent transactional state and writes it into the issue queue 216 alongwith every instruction from the transaction, execution of TBEGIN, TEND,and instructions before, within, and after the transaction can beperformed out-of order. It is even possible (though unlikely) that TENDis executed first, then the entire transaction, and lastly the TBEGINexecutes. Program order is restored through the GCT 232 at completiontime. The length of transactions is not limited by the size of the GCT232, since general purpose registers (GRs) 228 can be restored from thebackup register file 224.

During execution, the program event recording (PER) events are filteredbased on the Event Suppression Control, and a PER TEND event is detectedif enabled. Similarly, while in transactional mode, a pseudo-randomgenerator may be causing the random aborts as enabled by the TransactionDiagnostics Control.

Tracking for Transactional Isolation

The Load/Store Unit 280 tracks cache lines that were accessed duringtransactional execution, and triggers an abort if an XI from another CPU(or an LRU-XI) conflicts with the footprint. If the conflicting XI is anexclusive or demote XI, the LSU 280 rejects the XI back to the L3 272 inthe hope of finishing the transaction before the L3 272 repeats the XI.This “stiff-arming” is very efficient in highly contended transactions.In order to prevent hangs when two CPUs stiff-arm each other, aXI-reject counter is implemented, which triggers a transaction abortwhen a threshold is met.

The L1 cache directory 240 is traditionally implemented with staticrandom access memories (SRAMs). For the transactional memoryimplementation, the valid bits 244 (64 rows×6 ways) of the directoryhave been moved into normal logic latches, and are supplemented with twomore bits per cache line: the TX-read 248 and TX-dirty 252 bits.

The TX-read 248 bits are reset when a new outermost TBEGIN is decoded(which is interlocked against a prior still pending transaction). TheTX-read 248 bit is set at execution time by every load instruction thatis marked “transactional” in the issue queue. Note that this can lead toover-marking if speculative loads are executed, for example on amispredicted branch path. The alternative of setting the TX-read 248 bitat load completion time was too expensive for silicon area, sincemultiple loads can complete at the same time, requiring many read-portson the load-queue.

Stores execute the same way as in non-transactional mode, but atransaction mark is placed in the store queue (STQ) 260 entry of thestore instruction. At write-back time, when the data from the STQ 260 iswritten into the L1 240, the TX-dirty bit 252 in the L1-directory 256 isset for the written cache line. Store write-back into the L1 240 occursonly after the store instruction has completed, and at most one store iswritten back per cycle. Before completion and write-back, loads canaccess the data from the STQ 260 by means of store-forwarding; afterwrite-back, the CPU 114 (FIG. 2) can access the speculatively updateddata in the L1 240. If the transaction ends successfully, the TX-dirtybits 252 of all cache-lines are cleared, and also the TX-marks of notyet written stores are cleared in the STQ 260, effectively turning thepending stores into normal stores.

On a transaction abort, all pending transactional stores are invalidatedfrom the STQ 260, even those already completed. All cache lines thatwere modified by the transaction in the L1 240, that is, have theTX-dirty bit 252 on, have their valid bits turned off, effectivelyremoving them from the L1 240 cache instantaneously.

The architecture requires that before completing a new instruction, theisolation of the transaction read- and write-set is maintained. Thisisolation is ensured by stalling instruction completion at appropriatetimes when XIs are pending; speculative out-of order execution isallowed, optimistically assuming that the pending XIs are to differentaddresses and not actually cause a transaction conflict. This designfits very naturally with the XI-vs-completion interlocks that areimplemented on prior systems to ensure the strong memory ordering thatthe architecture requires.

When the L1 240 receives an XI, L1 240 accesses the directory to checkvalidity of the XI′ed address in the L1 240, and if the TX-read bit 248is active on the XI′ed line and the XI is not rejected, the LSU 280triggers an abort. When a cache line with active TX-read bit 248 isLRU′ed from the L1 240, a special LRU-extension vector remembers foreach of the 64 rows of the L1 240 that a TX-read line existed on thatrow. Since no precise address tracking exists for the LRU extensions,any non-rejected XI that hits a valid extension row the LSU 280 triggersan abort. Providing the LRU-extension effectively increases the readfootprint capability from the L1-size to the L2-size and associativity,provided no conflicts with other CPUs 114 (FIGS. 1 and 2) against thenon-precise LRU-extension tracking causes aborts.

The store footprint is limited by the store cache size (the store cacheis discussed in more detail below) and thus implicitly by the L2 268size and associativity. No LRU-extension action needs to be performedwhen a TX-dirty 252 cache line is LRU′ed from the L1 240.

Store Cache

In prior systems, since the L1 240 and L2 268 are store-through caches,every store instruction causes an L3 272 store access; with now 6 coresper L3 272 and further improved performance of each core, the store ratefor the L3 272 (and to a lesser extent for the L2 268) becomesproblematic for certain workloads. In order to avoid store queuingdelays, a gathering store cache 264 had to be added, that combinesstores to neighboring addresses before sending them to the L3 272.

For transactional memory performance, it is acceptable to invalidateevery TX-dirty 252 cache line from the L1 240 on transaction aborts,because the L2 268 cache is very close (7 cycles L1 240 miss penalty) tobring back the clean lines. However, it would be unacceptable forperformance (and silicon area for tracking) to have transactional storeswrite the L2 268 before the transaction ends and then invalidate alldirty L2 268 cache lines on abort (or even worse on the shared L3 272).

The two problems of store bandwidth and transactional memory storehandling can both be addressed with the gathering store cache 264. Thecache 264 is a circular queue of 64 entries, each entry holding 128bytes of data with byte-precise valid bits. In non-transactionaloperation, when a store is received from the LSU 280, the store cache264 checks whether an entry exists for the same address, and if sogathers the new store into the existing entry. If no entry exists, a newentry is written into the queue, and if the number of free entries fallsunder a threshold, the oldest entries are written back to the L2 268 andL3 272 caches.

When a new outermost transaction begins, all existing entries in thestore cache are marked closed so that no new stores can be gathered intothem, and eviction of those entries to L2 268 and L3 272 is started.From that point on, the transactional stores coming out of the LSU 280STQ 260 allocate new entries, or gather into existing transactionalentries. The write-back of those stores into L2 268 and L3 272 isblocked, until the transaction ends successfully; at that pointsubsequent (post-transaction) stores can continue to gather intoexisting entries, until the next transaction closes those entries again.

The store cache 264 is queried on every exclusive or demote XI, andcauses an XI reject if the XI compares to any active entry. If the coreis not completing further instructions while continuously rejecting XIs,the transaction is aborted at a certain threshold to avoid hangs.

The LSU 280 requests a transaction abort when the store cache 264overflows. The LSU 280 detects this condition when it tries to send anew store that cannot merge into an existing entry, and the entire storecache 264 is filled with stores from the current transaction. The storecache 264 is managed as a subset of the L2 268: while transactionallydirty lines can be evicted from the L1 240, they have to stay residentin the L2 268 throughout the transaction. The maximum store footprint isthus limited to the store cache size of 64×128 bytes, and it is alsolimited by the associativity of the L2 268. Since the L2 268 is 8-wayassociative and has 512 rows, it is typically large enough to not causetransaction aborts.

If a transaction aborts, the store cache 264 is notified and all entriesholding transactional data are invalidated. The store cache 264 also hasa mark per doubleword (8 bytes) whether the entry was written by a NTSTGinstruction—those doublewords stay valid across transaction aborts.

Millicode-Implemented Functions

Traditionally, IBM mainframe server processors contain a layer offirmware called millicode which performs complex functions like certainCISC instruction executions, interruption handling, systemsynchronization, and RAS. Millicode includes machine dependentinstructions as well as instructions of the instruction set architecture(ISA) that are fetched and executed from memory similarly toinstructions of application programs and the operating system (OS).Firmware resides in a restricted area of main memory that customerprograms cannot access. When hardware detects a situation that needs toinvoke millicode, the instruction fetching unit 204 switches into“millicode mode” and starts fetching at the appropriate location in themillicode memory area. Millicode may be fetched and executed in the sameway as instructions of the instruction set architecture (ISA), and mayinclude ISA instructions.

For transactional memory, millicode is involved in various complexsituations. Every transaction abort invokes a dedicated millicodesub-routine to perform the necessary abort operations. Thetransaction-abort millicode starts by reading special-purpose registers(SPRs) holding the hardware internal abort reason, potential exceptionreasons, and the aborted instruction address, which millicode then usesto store a TDB if one is specified. The TBEGIN instruction text isloaded from an SPR to obtain the GR-save-mask, which is needed formillicode to know which GRs 238 to restore.

The CPU 114 (FIG. 2) supports a special millicode-only instruction toread out the backup-GRs 224 and copy them into the main GRs 228. TheTBEGIN instruction address is also loaded from an SPR to set the newinstruction address in the PSW to continue execution after the TBEGINonce the millicode abort sub-routine finishes. That PSW may later besaved as program-old PSW in case the abort is caused by a non-filteredprogram interruption.

The TABORT instruction may be millicode implemented; when the IDU 208decodes TABORT, it instructs the instruction fetch unit to branch intoTABORT's millicode, from which millicode branches into the common abortsub-routine.

The Extract Transaction Nesting Depth (ETND) instruction may also bemillicoded, since it is not performance critical; millicode loads thecurrent nesting depth out of a special hardware register and places itinto a GR 228. The PPA instruction is millicoded; it performs theoptimal delay based on the current abort count provided by software asan operand to PPA, and also based on other hardware internal state.

For constrained transactions, millicode may keep track of the number ofaborts. The counter is reset to 0 on successful TEND completion, or ifan interruption into the OS occurs (since it is not known if or when theOS will return to the program). Depending on the current abort count,millicode can invoke certain mechanisms to improve the chance of successfor the subsequent transaction retry. The mechanisms involve, forexample, successively increasing random delays between retries, andreducing the amount of speculative execution to avoid encounteringaborts caused by speculative accesses to data that the transaction isnot actually using. As a last resort, millicode can broadcast to otherCPUs 114 (FIG. 2) to stop all conflicting work, retry the localtransaction, before releasing the other CPUs 114 to continue normalprocessing. Multiple CPUs 114 must be coordinated to not causedeadlocks, so some serialization between millicode instances ondifferent CPUs 114 is required.

As described above, during TM transactional execution, memory dataaccessing instructions that fetch memory operands, such as aload-and-add instruction, may mark the cache lines into which the memoryoperands are fetched as read-set cache lines of the transaction, via,for example, tx-read bit 248. A conflicting XI received, for example,from another CPU core requesting exclusive ownership of data in aread-set cache line of a transaction may cause the transaction to beaborted.

In a gathering store cache (store-accumulator) environment, memory dataaccessing instructions that store memory operands, such as, for example,add instructions with memory source and destination operands, store theoperands to L1 cache and a store-accumulator, such as gathering storecache 264. L1 cache lines to which operands are stored maybe marked aswrite-set cache lines of the transaction via, for example, tx-dirty bit252. During transactional execution, memory data stored to L1 cachelines and entries in gathering store cache 264 is not written through toL2 cache, for example, L2 cache 268, and shared cache, for example, L3cache 272, by the gathering store cache. Rather, evictions oftransactional stores from the gathering store cache 264 are suspendeduntil the transaction completes, at which time the buffered stores inthe gathering store cache are evicted to L2 cache 268 and, for example,through the L2 cache, to shared L3 cache 272. In an embodiment, L2 cache268 may be a write through, or store through, cache, in which writes tocache lines in L2 are, for example, at the same time, written to L3cache 272, or, for example, L2 cache writes updated lines to L3 cache.In other embodiments, L2 cache 268 may be a write back, or store-in,cache in which writes to lines in L2 cache are evicted, or cast out, toL3 cache.

Memory data addresses in XIs, which are associated with read requests tomemory from, for example, other processors, may be compared totransactional entries that are buffered in gathering store cache 264awaiting successful completion of the transaction. In one embodiment, ifa memory data address in a read or exclusive XI matches a memory dataaddress of data in a transactional entry buffered in gathering storecache 264, the XI may be rejected (“stiff-armed”) until the transactioncompletes successfully and any buffered write throughs in gatheringstore cache 264 are evicted to L2. For ease of description, cachecoherency requests, such as XIs, are described as being received fromother CPU cores or processors. However, those of skill in the art willrecognize that XIs may be received from other threads of a process, fromother processes executing on a single processor, from other processorsof a multi-processor CPU core, or from other CPU cores accessing commonmemory. Furthermore, other cache coherency protocols are well known inthe art that may not use XIs. Embodiments using such protocols areconsistent with the teaching herein wherein conflicts are detected usingsuch protocols.

In other embodiments, different store buffering cache arrangements canbe used. For example, in a system having private L1 and L2 caches and ashared L3 cache, the L1 and L2 caches may serve as store bufferingcaches, and transactional stores can be buffered in the L1 or L2 cachesprior to being stored to shared L3 cache upon successful completion ofthe transaction. For example, cache lines in the L1 and L2 caches can bemarked as read-set and write-set cache lines of a transaction. Duringexecution of the TM transaction, write-set cache lines of thetransaction in L1 and L2 cache are not evicted (written back) to theshared L3 cache. Upon successful completion of the TM transaction,write-set cache lines of the transaction are evicted to L3 cache in anatomic commit operation, and their read or write bits are cleared. In anembodiment, L2 is a write-back cache. Similar to the embodimentdescribed above, cache coherency requests from, for example, other CPUcores that may conflict with data from memory address stored in read-setcache lines of the transaction can cause the TM transaction to abort,and cache coherency requests for data from memory addresses stored inwrite-set cache lines can be rejected until the transaction completessuccessfully.

As described above, in one embodiment, a store-accumulator, such asgathering store cache 264, may serve two related purposes. Innon-transactional operation, gathering store cache 264, which may be acircular queue or first-in-first-out (FIFO) buffer for example, may actto reduce the store accesses to shared L3 cache 272, while stillallowing private caches, such as L1 cache 240, to execute“write-throughs” without excessive L3 cache store queuing delays. WhenLSU 280 initiates a store operation into a cache line in L1 cache 240from, for example a general register in GRs 228, the LSU, as part of thesame store operation, also stores the register value to gathering storecache 264. If gathering store cache 264 does not contain an entry thatincludes the memory address of the store passed by LSU 280, then a newline entry in gathering store cache 264 circular queue may be created toreceive the store passed by LSU 280. If gathering store cache 264 doescontain an entry that includes the address passed by LSU 280, then thebytes of the entry that correspond to the address of the store areupdated with the store. As bytes of an entry in gathering store cache264 are updated with a store, a byte-wise bit map associated with theentry is updated to indicate which bytes of the entry have been updated.In this manner, multiple stores from LSU 280 may be “gathered” intoentries of gathering store cache 264. If, for example, the number offree entries in gathering store cache 264 falls below a threshold value,updated bytes in the oldest entries in gathering store cache 264 may bewritten to L2 cache 268 and, through L2, to L3 cache 272. Thus, ratherthan writing each store to L1 cache 240 through to L2 cache 268, andthen, for example, through L2, to shared L3 cache 272, these“write-throughs” are gathered in gathering store cache 264, whichperiodically writes, or evicts, them to L2 cache 268, and, for example,through the L2 cache, to the L3 cache.

Gathering store cache 264 may also serve to speculatively buffer storesto, for example, L1 cache 240, that occur during a TM transaction.During execution of the TM transaction, eviction of transactional storesbuffered in the entries of gathering store cache 264 is suspended. Uponsuccessful completion of the TM transaction, the buffered transactionalstores are evicted, i.e., atomically committed, to, for example, L2cache 268, and, through the L2 cache, to public L3 cache 272.

FIG. 4 shows an embodiment of a multicore TM environment 400, inaccordance with an embodiment of the present disclosure, that includes aco-processor. TM multicore environment 400 is based on the environmentof FIGS. 1 and 2, described above, and includes CPU core 112A,co-processor 406, shared cache 124, and main memory 412, allinterconnected over interconnect 122. CPU core 112A includes CPU1 114A,instruction cache 116A, data cache 118A, store-accumulator 402A,read/track (RT) registers 404A, and interconnect control 120A.Co-processor 406 is coupled to interconnect 122 via an instructionchannel 408 and a data channel 410. Components of TM multicoreenvironment 400 having like reference numerals as components describedabove with reference to the environment of FIGS. 1 and 2 operate insubstantially the same manner. Although a single CPU core 112A isillustrated, the embodiments and concepts described may apply toimplementations that include multiple CPU cores coupled to interconnect122.

In one embodiment, co-processor 406 may be a cryptographic co-processorthat performs encryption and decryption functions. Co-processor 406 maybe dedicated to a particular CPU, such as CPU1 114A, or may be shared bytwo or more CPUs. In an embodiment, co-processor 406 is coupled tointerconnect 122 by any of well known interconnect mechanisms includinga DMA interface such as PCIe or logical or physical channels instructionchannel 408 and data channel 410. Cryptographic functions may beperformed by co-processor 406 through callable services that can becalled from an application program. For example, an application programmay call and pass parameters to a callable cryptographic service, whichis a co-processor operation performed on co-processor 406. An example ofa callable service may be a request to decrypt data located at anaddress range in main memory 412 to store unencrypted result data inanother address range in main memory 412. An application program maycontain a call to the decryption service, including parametersidentifying, for example, a decryption table, the main memory address ofthe input data to decrypt, and an address at which to store thedecrypted output data. Temporary results of a co-processor operation maybe stored, in an embodiment, in a program scratch area in main memory412, or in an embodiment, at an address in the memory of co-processor406. Information related to called the decryption service may be passedto co-processor 406 via any interface known in the art such as PCIe orinstruction channel 408, and data. The information associated with thecall may be passed to and from the co-processor via data channel 410.Co-processor 406 may fetch its input data directly from main memory 412or from shared cache 124.

During transactional execution of a transaction executing in the TMenvironment of FIG. 4, a fetch of input data needed for the co-processoroperation is performed by the co-processor from an address range in mainmemory in response to a service call from the transaction executing on aprocessor of CPU1 114A. This may result in the fetched co-processoroperation data not being in a cache line of data cache 118A that ismarked as a read-set cache line of the transaction. For example, duringtransactional execution of a TM transaction, a call may be made to thedecryption service on co-processor 406 to decrypt data at an address inmain memory. The call, which may include parameters containing theaddress or name of a decryption table, the main memory address of theinput data, and the address at which to store the decrypted output data,is passed from core 112A to co-processor 406 via interconnect control120A, interconnect 122, and instruction channel 408. Co-processor 406may fetch the input data, either from shared cache 124 or main memory412, via data channel 410.

If the co-processor operation input data is in a cache line of datacache 118A as the result of a an earlier fetch within the transaction,then the input data may be included in a read-set cache line of thetransaction, and will be monitored during execution of the transactionfor conflicting XIs.

If the co-processor operation input data is in a cache line of datacache 118A as the result of a fetch that occurred before execution ofthe transaction began, the cache line containing the data may not bemarked as a read-set cache line of the transaction. In this situation,if the data has not yet been accessed in the transaction, XIs from othertransactions that conflict with the input data will be handled in anon-TM manner—for example, the cache line in data cache 118A containingthe input data may be invalidated, but the transaction may not abort.

If the co-processor operation input data to co-processor 406 is not in acache line of shared cache 124, and thus not in data cache 118A,co-processor 406 may fetch the co-processor operation input data frommain memory 412 into a memory or cache of co-processor 406, and theinput data may not be included in a cache line of data cache 118A thatis marked as a read-set cache line of the transaction. In thissituation, XIs from, for example, other CPU cores that otherwise wouldconflict with the input data will not result in a cache hit in datacache 118A, and the transaction will not abort. It may be desirable ifanother mechanism allowed for the monitoring of co-processor operationmemory addresses to identify and respond to these conflicting accesses.

COP_DEFINE Instruction

In an embodiment of the disclosure, TM cache coherence logic allows fordata from main memory addresses fetched by a co-processor operationduring execution of a TM transaction that is not included in cache linethat is marked as a read-set cache line of a transaction to be treatedsimilarly to data that is contained in read-set cache lines of atransaction. For example, XIs that conflict with memory data fetched bya co-processor during execution of a TM transaction that is not includedin cache line that is marked as a read-set cache line of a transactionmay still cause a transaction to abort. In one embodiment, a newco-processor define (COP_DEFINE) range-setting instruction writesuser-specified addresses or address ranges into the newly defined set ofregisters, RT registers 404A. These registers may be contained, forexample, within the cache subsystem of data cache 118A, for example, thecache control subsystem of data cache 118A. For example, parameters ofthe COP_DEFINE instruction may include a single address, a begin addressand a length, or begin and end addresses. Indicator bits in theregisters of RT registers 404A can indicate the type address informationstored from the COP_DEFINE instruction parameters. The COP_DEFINEinstruction would typically be executed within a TM transaction justprior to a service call to co-processor 406 and would include the mainmemory 412 co-processor operation input addresses to be fetched by theco-processor.

During execution of a TM transaction, the TM cache coherence logicreceives XIs from, for example, other CPU cores and compares theaddresses in the XIs against the address and/or address ranges in RTregisters 404A, in addition to the addresses of data contained in theread-set cache lines of a transaction, to identify conflicts. If aconflict is detected between an XI and the address of data in a read-setcache line or an address in RT registers 404A, the transaction may beaborted. The abort handler may clear RT registers 404A, and may notifyco-processor 406, for example, via a return code, to abort an operationin process.

FIG. 5 is a flowchart depicting operational steps for performing aspectsof the COP_DEFINE instruction, in accordance with an embodiment of thedisclosure. A processor of CPU1 114A, for example, begins execution of aTM transaction (step 500). Within the transaction, a call is made to aco-processor service, for example, to be performed on co-processor 406.Prior to the call, CPU1 114A receives, via a COP_DEFINE instruction, theone or more main memory 412 addresses for the co-processor memoryoperands for the co-processor call (step 502). CPU1 114A stores thereceived co-processor memory operand addresses into, for example, aregister of RT registers 404A (step 504).

In the course of executing the TM transaction, core 112A receives cachecoherency requests, such as XIs, from, for example, other CPU corescoupled to interconnect 122 (step 506). Data cache 118A determines if anaddress in an XI conflicts with any data in the read-set cache lines ofthe transaction (decision step 508), or with any co-processor memoryoperand addresses stored in RT registers 404A by COP_DEFINE instructions(decision step 510). This may be performed, for example, by a cachecoherency conflict detector component of data cache 118A that comparesan address from an XI request asserted on interconnect bus 122 that hasbeen clocked into a hardware register of the cache coherency conflictdetector component, with addresses stored in the hardware registers ofRT registers 404A. Those of skill in the art will recognize that othermethods and implementations may be used to identify cache coherencyconflicts between an XI asserted on an interconnect bus and addressesand address ranges stored in registers.

If the XI does conflict with data in the read-set cache lines of thetransaction (decision step 508, “Y” branch), or with an address storedin RT registers 404A (decision step 510, “Y” branch), then thetransaction may be aborted (step 512), which may include clearing theregisters in RT registers 404A (step 514), and this processing ends. Ifno conflicts are found (decision steps 508 and 510, “N” branches), andthe transaction has not completed (decision step 516, “N” branch), theprocessor may, for example, receive and process additional cachecoherency requests (step 506). When the transaction completes (decisionstep 516, “Y” branch), this processing ends.

In another embodiment, an additional set of registers, for example,write-track (WT) registers, may be used to monitor the co-processoroperation memory store addresses. The WT registers, similar to the RTregisters, may reside, for example, in a CPU core, such as CPU core112A. For example, the COP_DEFINE instruction can include additionalparameters that identify addresses in processor memory to which outputoperands of a co-processor operation executed during a TM transactionwill stored. The WT registers may, for example, also include theaddresses to which the processor stores transactional stores. Forexample, when the processor executes a store operation, the memoryaddress of the store may be written to a WT register, and the data maybe written to a cache line in, for example, the L1 cache of theprocessor, which may be marked as a write-set cache line of thetransaction. The store may also be buffered to an entry in astore-accumulator, such as store-accumulator 402A or gathering storecache 264. In addition, stores to memory by the co-processor may also bespeculatively buffered. For example, as described in more detail below,co-processor transactional stores may be buffered in thestore-accumulator of the processor. In another embodiment, theco-processor may include a store-accumulator that operates substantiallyas described above in regards to the store-accumulator of a processor,and co-processor transactional stores may be buffered in thestore-accumulator of the co-processor. In another embodiment,co-processor transactional stores may be buffered in a data structure inmemory. For example, co-processor transactional stores may be insertedinto a linked-list data structure in processor memory that performs thefunctions of a store-accumulator, as described above.

In certain embodiments in which co-processor stores are buffered to, forexample, a store-accumulator of the processor, such as gathering storecache 264, data at the memory addresses of the stores may be prefetchedas exclusive into a private cache of the processor, for example, L1cache 240, and the L1 cache lines into which the prefetched data iswritten may be marked as write-set cache lines of the TM transaction.For example, as described above, in a TM transaction, a COP_DEFINEinstruction, executed just prior to executing a co-processor operation,may identify memory addresses to which the co-processor operation maystore. IDU 208, upon decoding the COP_DEFINE instruction, may cause L1cache 240 to prefetch the store addresses specified in the COP_DEFINEinstruction into, for example, L1 cache 240, and mark the L1 cache linesreceiving the store addresses as write-set cache lines of thetransaction. When the TM transaction in which the co-processor operationwas executed completes, the speculatively buffered co-processor storesin gathering store cache 264 may be evicted to high-level caches, suchas L2 cache 268, and L3 cache 272. In certain embodiments, uponcompletion of the TM transaction, the L1 cache 240 cache lines intowhich the prefetched data is written may be invalidated, and asubsequent processor fetch from the co-processor store address mayberesolved at L2 cache 268. In other embodiments, upon completion of theTM transaction, the speculatively buffered co-processor stores ingathering store cache 264 may be written to L1 cache 240 in addition tobeing written to L2 cache 268. For example, an indicator in thegathering store cache 264 entry for co-processor speculative stores mayindicate that the store is from a co-processor. Upon completion of theTM transaction, such stores may also be written to L1 cache 240.

The COP_DEFINE instruction may set real addresses or virtual addressesin the RT and WT registers, and hardware may translate RT and WT virtualaddresses to real addresses and save the real addresses for use in XIs.

During execution of the transaction, if a memory address in a read orexclusive XI received by the processor matches a memory address in a WTregister, the XI may be rejected until the transaction completes. Uponcompletion of the transaction, the buffered transactional stores of theprocessor and of the co-processor are written to higher-level cache,such as L2 cache 268 or shared cache 124, and made available to otherCPUs. If the transaction aborts, address entries in the WT registers andspeculative stores of the transaction from the processor andco-processor may be cleared or invalidated.

COP Stores to Store-Accumulator

In another aspect of the disclosure, stores to main memory addressesperformed by a co-processor, as a result, for example, of a service callto the co-processor during transactional execution of a processor, maybe stored directly to a store-accumulator of a processor, for example,gathering store cache 264. The co-processor stores may thus be treatedas speculative stores that, upon completion of the transaction, areevicted to higher level caches along with other buffered transactionalstores in the store-accumulator from the processor.

In certain embodiments, data at the memory addresses of the co-processorstores may be prefetched as exclusive into a private cache of theprocessor, for example, L1 cache 240, and the L1 cache lines into whichthe prefetched data is written may be marked as write-set cache lines ofthe TM transaction. For example, IDU 208, may identify memory addressesof the co-processor stores when decoding the co-processor callinstruction. IDU 208 may then cause L1 cache 240 to prefetch the storeaddresses specified in the co-processor call instruction into, forexample, L1 cache 240, and mark the L1 cache lines receiving the storeaddresses as write-set cache lines of the transaction. When the TMtransaction in which the co-processor operation was executed completes,the speculatively buffered co-processor stores in gathering store cache264 may be evicted to high-level caches, such as L2 cache 268, and L3cache 272. In certain embodiments, upon completion of the TMtransaction, the L1 cache 240 cache lines into which the prefetched datais written may be invalidated, and a subsequent processor fetch from theco-processor store address maybe resolved at L2 cache 268. In otherembodiments, upon completion of the TM transaction, the speculativelybuffered co-processor stores in gathering store cache 264 may be writtento L1 cache 240 in addition to being written to L2 cache 268. Forexample, an indicator in the gathering store cache 264 entry forco-processor speculative stores may indicate that the store is from aco-processor. Upon completion of the TM transaction, such stores mayalso be written to L1 cache 240.

FIG. 6 depicts a functional block diagram of components of a CPUenvironment 600 and a co-processor 602 associated with CPU 600, inaccordance with embodiments of the present disclosure. CPU 600 of FIG. 6is based on the embodiment describe with respect to FIG. 3, withelements having like reference numbers performing substantially the samefunctions in substantially the same manner, except as may be describedbelow. A co-processor 602 is coupled to gathering store cache 264 suchthat co-processor 602 may treat gathering store cache 264 as a componentof its own environment. As will be appreciated by those of skill in theart, co-processor 602 may be coupled to gathering store cache 264, andother components of CPU 600, by various implementations. For example,co-processor 602 and gathering store cache 264 may both be coupled to aninterconnect bus, (not shown), that allows co-processor 602 to exchangedata and other information directly with gathering store cache 264. Inaddition, co-processor 602 may receive data and instructions associatedwith co-processor operations from CPU 600 over the interconnect bus. Inanother embodiment, co-processor information is passed by way of sharedmemory, shared between the processor and co-processor. Those of skill inthe art will recognize that other implementations to connectco-processor 602 to gathering store cache 264, and to other componentsof CPU 600, are possible. Those of skill in the art will also recognizethat the control logic of gathering store cache 264 may requirearbitration logic, or similar, to allow stores from both co-processor602 and LSU 280.

As described above, during execution of a TM transaction, memory datastored to a cache line in L1 cache, for example, L1 cache 240, is alsostored to and buffered in, for example, gathering store cache 264 untilthe transaction completes. Addresses in read and exclusive XIs receivedfrom, for example, other CPU cores are compared to addresses intransactional store entries in gathering store cache 264. In thismanner, speculative stores to shared memory, for example, L3 cache 272,are hidden from, for example, other CPU cores until the atomic commit ofthe buffered transactional stores in gathering store cache 264 uponsuccessful completion of the transaction. Traditionally, becausetransactional stores to main memory locations by co-processor 602 arenot written to data cache 118A, they may not be buffered in gatheringstore cache 264. Rather, for example, a co-processor may write itsstores directly to main memory. As a result, transactional stores tomain memory by co-processor 602 may not be hidden from, for example,other CPU cores pending successful completion of the transaction, andmay not be available for compares against XIs received, for example,from other CPU cores.

In an embodiment, memory stores by co-processor 602 as a result of acall to the co-processor from a CPU executing a TM transaction arestored to a store-accumulator of the CPU, such as gathering store cache264, and are buffered as speculative stores of the transaction. Uponcompletion of the transaction, all buffered stores of the transaction inthe store-accumulator are evicted to higher level caches, such as L2cache 268 and, for example, through L2, to L3 cache 272, where thestores are made available to, for example, other CPU cores.

In the embodiment of FIG. 6, gathering store cache 264 operates insubstantially the same manner as described above, with the exceptionthat the gathering store cache may receive stores from both LSU 280 ofCPU 600, and co-processor 602 during transactional execution. Asdescribed above, if gathering store cache 264 does not contain an entrythat includes the memory address of the received store, a new line entryin gathering store cache 264 may be created to receive the store. Ifgathering store cache 264 does contain an entry that includes theaddress of the received store, the bytes of the entry that correspond tothe address range of the store are updated with the store. As describedabove, during transactional execution, transactional stores in theentries of gathering store cache 264 are buffered as speculative storesof the transaction, and eviction of transactional stores is suspended.When the transaction completes, the buffered transactional stores in thegathering store cache 264 are evicted to L2 cache 268 and, for example,through the L2 cache, to shared L3 cache 272.

FIG. 7 is a schematic block diagram illustrating simplified operation ofa processor and a co-processor with respect to stores to astore-accumulator of the processor. A CPU 700 includes a generalregister GR 702, a load-store unit LSU 704, a store-accumulator 710, anda private L2 cache 716. LSU 704 includes L1 cache 706. A co-processor722 is coupled to store-accumulator 710 of CPU 700, and a public L3cache 726 is coupled to L2 cache 716 of CPU 700. Co-processor 722includes a general register 724.

General registers 702 and 724 may be, for example, 64-bit hardwaregeneral purpose registers, represented by the diagonal hatched patterns.L1 cache 706 includes a cache line 732, of a plurality of cache lines,which includes addressable storage locations, for example, storagelocation 708, having a size, or length, corresponding to the size ofgeneral registers 702 and 724, for example, 64 bits. Similarly,store-accumulator 710 includes an entry 734, of a plurality of entries,with storage locations, such as storage locations 712 and 714; L2 cache716 includes a cache line 736, of a plurality of cache lines, withstorage locations, such as storage locations 718 and 720; and L3 cache726 includes a cache line 738, of a plurality of cache lines, withstorage locations, such as storage locations 728 and 730. It should beappreciated that instruction operands may not necessarily be 64 bit (8byte) operands. They may be any number of bytes and may not be alignedon an 8 byte boundary.

In an exemplary embodiment, when CPU 700 is executing a TM transaction,stores executed by LSU 704 store, for example, data in general registersof the CPU, for example, data in GR 702, into a location in a cache linein L1 cache 706, for example, location 708 of cache line 732. LSU 704,in the same store operation, also stores the data in GR 702 into alocation of an entry in store-accumulator 710, for example, location 712of entry 734. Co-processor 722, performing an operation called by the TMtransaction, may execute a store to memory by performing a store to alocation of an entry of store-accumulator 710, for example, location 714of entry 734 of store-accumulator 710.

As described above, during execution of the transaction, transactionalstores to store-accumulator 710 are buffered, and eviction oftransactional stores in entries of store-accumulator 710 are suspendeduntil the TM transaction ends. During execution of the transaction, if amemory data address in a read or exclusive XI received by CPU 700matches a memory data address in a transactional store buffered ingathering store-accumulator 710, either from CPU 700 or co-processor722, the XI may be rejected (“stiff-armed”) until the transactioncompletes successfully and any buffered transactional stores instore-accumulator 710 are evicted.

When the transaction completes, the transactional stores in entries ofstore-accumulator 710 may be evicted to higher level caches, such as L2cache 716. For example, the transactional store of the data from GR 702in location 712 of entry 734 of store-accumulator 710, and thetransactional store of the data from GR 724 in location 714 of entry 734of store-accumulator 710 may be evicted to locations 718 and 720 ofcache line 736 of L2 cache 716, respectively. In an embodiment, only theupdated bytes of an evicted entry of store-accumulator 710 need bewritten to L2. Preferably, as opposed to a traditional cache line, theaccumulator doesn't load a line of data when an entry is initiated.Rather, only store operand bytes from the LSU are written to theaccumulator. The transactional stores in L2 cache 716, for example thetransactional stores in cache line 736 at locations 718 and 720, mayalso, for example, be evicted from, or written through, to shared L3cache 726, for example, to cache line 738. This eviction may beperformed, for example, at the typical cache line level, where theentire cache line 736 is evicted in a single operation to L3 cache 726,for example, to cache line 738.

If the transaction aborts, the transactional stores buffered instore-accumulator 710, for example, data stored at locations 712 and 714of entry 734 in store-accumulator 710, are not evicted to higher levelcaches, such as L2 cache 716. In an embodiment, the transaction aborts,and all transactional stores in store-accumulator 710 are, for example,cleared by, for example, either invalidating the entry or clearing thebyte-wise indicator bits of entries that are associated withtransactional stores.

FIG. 8 is a flowchart depicting operational steps for performingtransactional stores by a co-processor associated with a CPU executingthe transaction, in accordance with an embodiment of the disclosure. ACPU, for example, CPU 700, begins execution of a TM transaction (step800). Within the transaction, a call is made to a co-processor, forexample, co-processor 722, for a co-processor operation to be performed(step 802). Co-processor 722 performs the co-processor operation, and,instead of writing the memory operand data from its co-processor generalregister GR 724 to, for example, shared memory, stores the memoryoperand data to, for example, a store-accumulator 710 (step 804) of thecalling processor.

If the TM transaction completes (decision step 806, “Y” branch),speculative transactional stores that are buffered in store-accumulator710, including ones stored by co-processor 722, are evicted to, forexample, L2 cache 716 (step 808). If the TM transaction does notcomplete successfully (decision step 806, “N” branch), all speculativetransactional stores for the transaction that are buffered instore-accumulator 710 are, for example, cleared or invalidated (step810), and this processing ends.

FIG. 9 is a flowchart depicting operational steps for monitoring, by aprocessor having a cache, addresses accessed by a co-processorassociated with the processor during transactional execution of atransaction by the processor, in accordance with an embodiment of theinvention. The processor begins execution of a TM transaction (step900). The processor receives a memory address range of data that aco-processor may access to perform a co-processor operation (step 902).In an embodiment, the processor may receive the memory address rangeduring processing of the parameters of a range-setting instruction (904)that is executed by the processor as part of executing the TMtransaction. The processor saves the memory address range (step 906). Inan embodiment, the memory address range may be saved to one or moreprocessor hardware registers (908). The processor receives a cachecoherency request (step 910). In an embodiment, the cache coherencyrequest may be received over a multi-processor bus (912). A cachecoherency conflict detector (914) may detect whether the cache coherencyrequest, as may be asserted on multi-processor bus (912), conflicts withthe co-processor operation memory address range, as may be saved inprocessor hardware registers (908). If the cache coherency requestconflicts with an address in the saved memory address range (decisionstep 916, “Y” branch), the processor aborts the transaction (step 918)and this processing ends. If the cache coherency request does notconflicts with an address in the saved memory address range (decisionstep 916, “N” branch), and the transaction has not completed (decisionstep 920, “N” branch), the processor may, for example, receive andprocess additional cache coherency requests (step 910). When thetransaction completes decision step 920, “Y” branch), this processingends.

FIG. 10 depicts a block diagram of components of an embodiment of acomputing device 900 that may include the multicore transactional memoryenvironment of FIG. 1, the CPU core of a multicore transactional memoryenvironment of FIG. 2, the components of the CPU of FIG. 3, thecomponents of the CPU and co-processor of FIG. 6, and/or the componentsof the CPU and processor of FIG. 7, in accordance with one or moreembodiments of the disclosure. It should be appreciated that FIG. 10provides only an illustration of one implementation and does not implyany limitations with regard to the environments in which differentembodiments may be implemented. Many modifications to the depictedenvironment may be made within the scope of the different embodimentsdescribed herein.

Computing device 1000 can include one or more processors 1002, one ormore computer-readable RAMs 1004, one or more computer-readable ROMs1006, one or more computer readable storage media 1008, device drivers1012, read/write drive or interface 1014, and network adapter orinterface 1016, all interconnected over a communications fabric 1018.Communications fabric 1018 can be implemented with any architecturedesigned for passing data and/or control information between processors(such as microprocessors, communications and network processors, etc.),system memory, peripheral devices, and any other hardware componentswithin a system.

One or more operating systems 1010, and application programs 1028 may bestored on one or more of the computer-readable tangible storage devices1008 for execution by one or more of the processors 1002 via one or moreof the RAMs 1004 (which typically include cache memory). In theillustrated embodiment, each of the computer readable storage media 1008can be a magnetic disk storage device of an internal hard drive, CD-ROM,DVD, memory stick, magnetic tape, magnetic disk, optical disk, asemiconductor storage device such as RAM, ROM, EPROM, flash memory orany other computer readable storage media that can store a computerprogram and digital information. Computing device 1000 can also includea R/W drive or interface 1014 to read from and write to one or moreportable computer readable storage media 1026.

Computing device 1000 can also include a network adapter or interface1016, such as a TCP/IP adapter card or wireless communication adapter.Information, such as application program(s) 1028, can be downloaded tocomputing device 1000 from an external computer or external storagedevice via a network (for example, the Internet, a local area network orother, wide area network or wireless network) and network adapter orinterface 1016. From the network adapter or interface 1016, theinformation may loaded into computer readable storage media 1008. Thenetwork may comprise copper wires, optical fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers.

Computing device 1000 can also include a display screen 1020, a keyboardor keypad 1022, and a computer mouse or touchpad 1024. Device drivers1012 may interface to display screen 1020 for imaging, to keyboard orkeypad 1022, to computer mouse or touchpad 1024, or to display screen1020 for pressure sensing of alphanumeric character entry and userselections. The device drivers 1012, R/W drive or interface 1014 andnetwork adapter or interface 1016 can comprise hardware and software(stored in computer readable storage media 1008 and/or ROM 1006).

The present embodiments may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent embodiments.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present embodiments may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Java, Smalltalk, C++ or the like,and conventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present embodiments.

Aspects of the present embodiments are described herein with referenceto flowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

Although preferred embodiments have been depicted and described indetail herein, it will be apparent to those skilled in the relevant artthat various modifications, additions, substitutions and the like can bemade without departing from the spirit of the invention, and these are,therefore, considered to be within the scope of the invention, asdefined in the following claims.

What is claimed is:
 1. A method for monitoring, by a processor having acache, addresses in a main memory accessed directly by a co-processorassociated with the processor during transactional execution of atransaction by the processor, the method comprising: executing, by theprocessor, a transactional memory (TM) transaction, the executingcomprising: executing a co-processor address range-setting instruction,wherein the co-processor address range setting instruction includes aparameter for a user-specified main memory address range that is not ina read-set of the TM transaction, the co-processor address range-settinginstruction execution comprising: obtaining, in the user-specifiedparameter of the co-processor address range-setting instruction, themain memory address range of data that the co-processor may access; andstoring, directly by the processor, the main memory address range ofdata in one or more hardware registers; and receiving, by the processor,a cache coherency request; in response to determining, by the processor,that the cache coherency request does not conflict with an address rangein the read-set of the TM transaction, and that the cache coherencyrequest conflicts with the stored main memory address range, abortingthe TM transaction.
 2. A method in accordance with claim 1: whereinstoring the main memory address range further comprises including anindicator indicating that the stored main memory address range is anactive address range; wherein receiving the cache coherency request thatconflicts further comprises receiving a cache coherency request thatconflicts with an address in the stored main memory address range thatis indicated as being an active address range; and wherein aborting theTM transaction further comprises changing the indicator to indicate thatthe stored main memory address range is not an active address range. 3.A method in accordance with claim 1, wherein the one or more hardwareregisters are contained in a cache subsystem of a cache.
 4. A method inaccordance with claim 1, wherein receiving a conflicting cache coherencyrequest comprises receiving a conflicting cache coherency request on amulti-processor bus.
 5. A method in accordance with claim 1, wherein aconflicting cache coherency request is a request indicating an intent tostore data to an address in the memory address range stored in the oneor more hardware registers.